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Features
* ARM7TDMI(R) ARM(R) Thumb(R) Processor Core
- In-Circuit Emulator, 36 MHz operation
* Ethernet Bridge * * * * * * * * * *
- Dual Ethernet 10/100 Mbps MAC Interface - 16-Kbyte Frame Buffer 1 K-Byte Boot ROM, Embedding a Boot Program - Enable Application Download from DataFlash(R) External Bus Interface - On-chip 32-bit SDRAM Controller - 4-Chip Select Static Memory Controller Multi-level Priority, Individually Maskable, Vectored Interrupt Controller Three 16-bit Timer/Counters Two UARTs with Modem Control Lines Serial Peripheral Interface (SPI) Two PIO Controllers, Managing up to 48 General-purpose I/O Pins Available in a 256-ball BGA Package Power Supplies - VDDIO 3.3V nominal - VDDCORE and VDDOSC 1.8V nominal -40C to + 85C Operating Temperature Range
AT91(R) ARM(R) Thumb Microcontrollers AT91C140
Description
The AT91C140 is a member of the Atmel AT91 16- and 32-bit microcontroller family based on the ARM7TDMI processor core. This processor has a high performance 32-bit RISC architecture with a high density 16-bit instruction set and very low power consumption. In addition, the AT91C140 integrates a double Ethernet 10/100 base-T MAC capable of operating as an Ethernet bridge, thus making it ideally suited for networking applications. It supports a wide range of memory devices such as SDRAM, SRAM and Flash and embeds an extensive array of peripherals. The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with an expansive assortment of peripheral functions and low-power oscillators and PLL on a monolithic chip, the Atmel AT91C140 is a powerful microcontroller that provides a highly flexible and cost effective solution to many networking applications.
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Block Diagram
Figure 1. AT91C140 Block Diagram
JTAG Debug Interface
ICE
ARM7TDMI Processor
Boot ROM
External Bus Interface MII PHY Interface Ethernet 10/100 Mbps MAC Interface
ASB/ASB Bridge
SDRAMC 16- or 32-bit data Memory Bus
MII PHY Interface
Ethernet 10/100 Mbps MAC Interface
SMC 16k Bytes SRAM
Peripheral Data Controller Peripheral Bridge OSC. PLL Interrupt and Fast Interrupt Advanced Interrupt Controller USART A
System Controller
SPI
Serial Peripherals Boot DataFlash
Serial Port
USART B I/O Lines PIO Controller A Timer/Counter 0 I/O Lines PIO Controller B Timer/Counter 1 Timer/Counter 2
Serial Port
PWM Signals PWM Signals PWM Signals
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Pinout
256-ball BGA Package Pinout
Table 1. Pinout for 256-ball BGA Package
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 Signal Name GND PB9 PB4 PB1 NDSRB NRSTB RXDB NDSRA TXDA PA2 PA3 PA6 PA10 PA13 PA15 PA19 NC(1) PA23 TDO NC(1) VDDIO PB8 PB7 PB3 PB0 NDTRB TXDB NDCDA NRSTA PA1 PA5 PA7 PA11 VDDCORE PA16 Pin B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 Signal Name TDI NC(1) NC(1) PB10 PA28 DBW32 PB6 PB2 NRIB NCTSB NRIA NCTSA PA0 PA4 PA8 PA12 PA14 PA18 PA21 TCK NC(1) NC(1) PA31 PB11 PA27 PA26 GND PB5 VDDIO NDCDB GND NDTRA RXDA VDDIO PA9 Pin D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 Signal Name VDDIO PA24 GND PA29 VDDCORE IRQ1 NC(1) GND GND PA25 PA30 TST IRQ0 NC(1) PB13 PB12 GND VDDIO VDDIO FIQ NC(1) SPCK MA_COL PB15 PB14 NTRST NRST PA22 MOSI MISO MA_TXD0 MA_TXER MA_CRS GND GND Pin H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 Signal Name NSOE MA_TXEN MA_TXD3 MA_TXD2 MA_TXD1 NWR NWE3 NC(1) NWE2 MA_RXD0 MA_TXCLK NC(1) VDDIO NWE1 NWE0 NCE3 NCE2 MA_RXD1 MA_RXD2 MA_RXD3 MA_RXER VDDIO NCE0 NC(1) NCE1 MA_RXCLK VDDCORE MA_RXDV MA_MDC PLLRC NC(1) XTALOUT XTALIN MA_MDIO MA_LINK
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Table 1. Pinout for 256-ball BGA Package (Continued)
Pin B16 B17 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 Signal Name PA20 TMS GND DQM3 VDDCORE VDDOSC MB_CRS VDDCORE MB_TXD0 MB_TXD3 RAS DQM0 DQM1 DQM2 MB_TXER MB_TXD1 MB_TXEN VDDIO VDDIO SDA10 CAS WE MB_TXD2 MB_TXCLK MB_RXD1 MB_RXER D28 D31 SDCK Pin D13 D14 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 Signal Name GND PA17 SDCS MB_RXD0 MB_RXD2 MB_RXCLK GND A1 VDDIO A8 GND A17 VDDIO D3 D7 GND D16 VDDIO D22 GND D27 NC(1) D30 MB_RXD3 MB_RXDV NC(1) A0 A4 A7 Pin H18 H19 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 Signal Name VDDIO VDDCORE A11 A14 A18 A22 D2 D6 D10 D14 NC(1) D19 D23 D26 NC(1) D29 MB_MDC NC(1) NC(1) MB_LINK A5 A9 A12 A15 A19/BA0 A21 D1 D5 D9 Pin N3 N4 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name MB_COL GND D12 VDDCORE D17 D20 D24 VDDIO NC(1) NC(1) MB_MDIO A2 A3 A6 A10 A13 A16 A20/BA1 A23 D0 D4 D8 D11 D13 D15 D18 D21 D25 NC(1)
Note:
1. NC Balls should be left unconnected.
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Mechanical Overview of the 256-ball BGA Package
Figure 2 below shows the orientation of the 256-ball BGA Package. For a detailed mechanical description, see "Mechanical Characteristics and Packaging" on page 162. Figure 2. 256-ball BGA Package Orientation (Top View)
A B C D E F G H J K L M N P R T U V W Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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Peripheral Multiplexing on PIO Lines
The AT91C140 features two PIO Controllers, PIOA and PIOB, multiplexing I/O lines of the peripheral set. The PIO Controller A manages 32 I/O lines, PA0 to PA31. The PIO Controller B manages only 16 I/O lines, PB0 to PB15. Each I/O line of a PIO Controller can be multiplexed with a peripheral I/O. Multiplexing of the PIO Controller A is given in Table 2 on page 7. Multiplexing of the PIO Controller B is given in Table 3 on page 8.
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PIO Controller A Multiplexing
Table 2. Multiplexing on PIO Controller A
I/O Line Name PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 NPCS0 Serial Peripheral Chip Select 0 I/O NPCS2 NPCS3 TCLK2 TIOA2 TIOB2 ACLKO Serial Peripheral Chip Select 2 Serial Peripheral Chip Select 3 Timer Counter Clock 2 Timer Counter I/O Line A 2 Timer Counter I/O Line B 2 ARM System Clock Output Output Input I/O I/O Output TCLK0 TIOA0 TIOB0 SCKA NPCS1 Timer Counter Clock Input 0 Timer Counter I/O LIne A 0 Timer Counter I/O LIne B 0 UART A Serial Clock Serial Peripehral Chip Select 1 Input I/O I/O I/O Output Signal Name Peripheral Description Type
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PIO Controller B Multiplexing
Table 3. Multiplexing on PIO Controller B
I/O Line Name PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 NRIA UART A Ring Indicator Input Signal Name TCLK1 TIOA1 TIOB1 Peripheral Description Timer Counter Clock Input 1 Timer Counter I/O LIne A 1 Timer Counter I/O LIne B 1 Type Input I/O I/O
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Signal Description
Table 4. Signal Description
Block Signal Name VDDIO VDDCORE Power Supplies VDDOSC GND A0-A23 External Bus Interface D0-D31 SDCK DQM0-DQM3 SDCS Synchronous Dynamic Memory Controller SDA10 RAS CAS WE BA0-BA1 NCE0-NCE3 NWE0-NWE3 Static Memory Controller NSOE NWR PIO Controller A PIO Controller B PA0-PA31 PB0-PB15 TCLK0-TCLK2 Timer Counter TIOA0-TIOA2 TIOB0-TIOA2 MISO MOSI Serial Peripheral Interface SPCK NPCS0/NSS NPCS1-NPCS3 Output Enable Memory Block Write Enable PIO Controller A I/O Lines PIO Controller B I/O Lines Timer Counter Clock 0 to 2 Timer Counter I/O Line A 0 to 2 Timer Counter I/O Line B 0 to 2 Master In/Slave Out Master Out/Slave In Serial Clock Peripheral Chip Select 0/Slave Select Peripheral Chip Select 1 to 3 Output Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Data Bus SDRAM Clock SDRAM Byte Masks SDRAM Chip Select SDRAM Address Line 10 Row Address Strobes Column Address Strobes Write Enable Bank Address Line Chip Selects Byte Select/Write Enable Input/Output Output Output Output Output Output Output Output Output Output Output PLL and Oscillator Power Supply Ground Address Bus Output Function I/O Lines Power Supply Device Core Power Supply Type
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Table 4. Signal Description (Continued)
Block Signal Name RXDA-RXDB TXDA-TXDB NRTSA-NRSTB NCTSA-NCTSB UART A and UART B NDTRA-NDTRB NDSRA-NDSRB NDCDA-NDCDB NRIA-NRIB MA_COL MA_CRS MA_TXER MA_TXD0-MA_TXD3 MA_TXEN MA_TXCLK MAC A Interface MA_RXD0-MA_RXD3 MA_RXER MA_RXCLK MA_RXDV MA_MDC MA_MDIO MA_LINK MB_COL MB_CRS MB_TXER MB_TXD0-MB_TXD3 MB_TXEN MB_TXCLK MAC B Interface MB_RXD0-MB_RXD3 MB_RXER MB_RXCLK MB_RXDV MB_MDC MB_MDIO MB_LINK Data Terminal Ready Data Set Ready Data Carrier Detect Ring Indicator MAC A Collision Detect MAC A Carrier Sense MAC A Transmit Error MAC A Transmit Data Bus MAC A Transmit Enable MAC A Transmit Clock MAC A Receive Data Bus MAC A Receive Error MAC A Receive Clock MAC A Receive Data Valid MAC A Management Data Clock MAC A Management Data Bus MAC A Link Interrupt MAC B Collision Detect MAC B Carrier Sense MAC B Transmit Error MAC B Transmit Data Bus MAC B Transmit Enable MAC B Transmit Clock MAC B Receive Data Bus MAC B Receive Error MAC B Receive Clock MAC B Receive Data Valid MAC B Management Data Clock MAC B Management Data Bus MAC B Link Interrupt Output Input Input Input Input Input Output Output Output Input Input Input Input Output Output Input/Output Input Input Input Output Output Output Input Input Input Input Output Output Input/Output Input Function Receive Data Transmit Data Ready to Send Clear to Send Type Input Output Output Input
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Table 4. Signal Description (Continued)
Block Signal Name NTRST TCK In-Circuit Emulator TMS TDI TDO NRST FIQ IRQ0-IRQ1 PLLRC Miscellaneous XTALIN XTALOUT TST DBW32 ACLKO Function Test Reset Test Clock Test Mode Select Test Data Input Test Data Output Reset Fast Interrupt Interrupt Lines PLL RC Filter Crystal Input External Crystal Test Mode External Data Bus Width for CS0 (1 = 32 bits) ARM Clock Output Type Input Input Input Input Output Input Input Input Analog Analog Analog Input Input Output
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ARM7TDMI Core
The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture is Von Neumann load/store architecture, characterized by a single data and address bus for instructions and data. The CPU has two instruction sets: the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum performance. Thumb instructions are 16-bit wide and give maximum code density. Instructions operate on 8-bit, 16-bit and 32-bit data types. The CPU has seven operating modes. Each operating mode has dedicated banked registers for fast exception handling. The processor has a total of 37 32-bit registers, including six status registers.
Power Supplies
The AT91C140 has three types of power supply pins: * * * VDDCORE pins power the core, including the ARM7TDMI processor, the memories and the peripherals; voltage is between 1.65V and 1.95V, 1.8V nominal. VDDIO pins power the I/O lines, including those of the External Bus Interface and those of the peripherals; voltage is between 3V and 3.6V, 3.3V nominal. VDDOSC pins power the PLL and oscillator cells; voltage is between 1.65V and 1.95V, 1.8V nominal.
Ground pins are common to all power supplies.
System Controller
The AT91C140 features a System Controller that takes care of and controls: * * * * The Test Mode The Reset The System Clocks The Chip Identifier
The System Controller manages the reset of all the system and integrates a clock generator, made up of an oscillator and a PLL.
Test
The AT91C140 features a test pin (TST). This pin must be tied low for normal operations. Using the AT91C140 with the TST pin at a high level might lead to unpredictable results.
Reset Controller
NRST Pin The AT91C140 is reset by asserting the NRST pin low. It should be asserted for a time adequate to ensure the startup of the oscillator on a power on, and at least 1 ACLK cycle for a warm reset. As the ACLK switches on the 31,25kHz (assuming the crystal is at 16 MHz) as soon as the reset is asserted, it must remain low for at least 32 s. The first instruction fetch happens 10 ACLK cycles after the reset releases. A reset initializes the user interface registers to their default states as defined in the peripheral sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter and the Current Program Status Register, the ARM processor registers do not have defined reset states. When NRST is active, the inputs of the AT91C140 must be held at valid logic levels to reduce the power consumption to a minimum.
System Reset
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Boot Memory and Remap Command When NRST is released, the PA0 pin is sampled to determine if the ARM processor should boot from internal ROM or from external memory connected to NCE0. The details of the boot operations are described in "Memory Controller (MC)" on page 17. The Boot Program is described in "Boot Program" on page 24. After a reset, the RM bit in the Mode Register reflects the state of the PA0 pin. Then, writing this bit at 1 removes the ROM from the address 0. Writing it at 0 remaps the ROM at address 0x0.
Clock Generator
The AT91C140 features a Clock Generator based on a 16 MHz oscillator and a PLL. It provides all the clocks of the system, including a clock signal named ACLK, to the ARM processor, to the memory controller and to the External Bus Interface and to all the embedded peripherals The ACLK signal is also provided on the ACLKO pin, through PIO Controller A. Figure 3 below shows the architecture of the Clock Generator.
Figure 3. Clock Generator
LP LPCS Counter and Control Logic DIV SA DIV7
1 0 1
RDY
XTALIN 16 MHz Crystal XTALOUT
ACLK
16MHz Oscillator
LP
DIV6
0
ACLKO
PLLRC
PLL
x15
240 MHz
After the reset, the ACLK clock is running at 31.25 kHz. The user can program the LPCS field to speed the boot sequence. The ACLKST (ARM Clock Status) bit reflects the clock being used for the ARM. When read at 0, ACLK is 40 MHz if SA is 0 and 34.3 MHz if SA is 1. When read at 1, ACLK is at a frequency according to the value programmed in the LPCS field in the System Mode Register (SYS_MR).
Chip ID
The System Controller features a Chip ID Register that reads a value of 0x00010221
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System Controller User Interface
Base Address: 0xFF00 0000. Table 5. System Controller Register Mapping
Offset 0x0 0x4 0x8 0xC Register Name SYS_MD SYS_ID Reserved SYS_CLKF System Clock Status Register Read-only 0x0000001 Register Description System Mode Register System ID Register Access Read/Write Read-only Reset Value 0x0000 034x 0x0001 0221
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System Mode Register
Register Name: SYS_MD Access: Read/Write
31 - 23 - 15 - 7 SA 30 - 22 - 14 0 6 LP 29 - 21 - 13 - 5 - 28 - 20 - 12 0 4 - 27 - 19 - 11 - 3 0 26 - 18 - 10 - 2 - 25 - 17 - 9 LPCS 1 0 0 RM 24 - 16 - 8
* RM: Remap 0 =The ROM is mapped only at its normal address. 1 =The ROM is mapped at its address and at address 0x0. * LP: Low Power Mode 0 =The PLL is enabled and ACLK is the output of the PLL divided by 6 or 7. 1 =The PLL is disabled and ACLK is defined by LPCS. * SA: Slow ARM 0 =The ARM divider is 6. 1 =The ARM divider is 7. * LPCS: Low Power Clock Select
LPCS 0 0 1 1 0 1 0 1 Divisor 2 16 64 512 ACLK 8 MHz 1 MHz 250 kHz 31,25 kHz
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System ID Register
Register Name: Access:
31 0 23 0 15 0 7 0
SYS_ID Read-only
30 0 22 0 14 0 6 0 29 0 21 0 13 0 5 1 28 0 20 0 12 0 4 0 27 0 19 0 11 0 3 0 26 0 18 0 10 0 2 0 25 0 17 0 9 1 1 0 24 0 16 1 8 0 0 1
System Clock Status Register
Register Name: Access:
31 - 23 - 15 - 7 -
SYS_CLKF Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 ACLKST
* ACLKST: ARM Clock Status 0 = ARM Clock currently using the 240 MHz source (PLL). 1 = ARM Clock currently using the 16 MHz source (oscillator).
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Memory Controller (MC)
Architecture
The AT91C140 architecture is made up of two Advanced System Buses, the ARM ASB and the MAC ASB. Both handle a single memory space. The ARM ASB handles the access requests of the ARM7TDMI and the PDC. It also handles the access requests coming from the MAC ASB. It connects with the External Bus Interface, the Peripheral Bridge and the Internal Memories. It also connects with the MAC ASB. The MAC ASB handles the access requests of the DMAs of both Ethernet MACs. It also handles the access requests coming from the the ARM ASB. It connects essentially with the Frame Buffer, but also connects with the ARM ASB. The major advantage of this double-ASB architecture is that the Ethernet traffic does not occupy the main ASB bandwidth, ensuring that the ARM7TDMI can perform at its maximum speed while the Ethernet traffic goes through the Frame Buffer. The AT91C140 architecture is shown in Figure 4. Figure 4. AT91C140 Memory Controller Architecture
PA0 Memory Controller
ARM ASB ARM7TDMI Processor Internal ROM Main Bus Arbiter External Bus Interface ASB-ASB Bridge
Peripheral Data Controller
From Master to Slave
MACA DMA Secondary Bus Arbiter MACB DMA MAC ASB
Peripheral Bridge
APB
SRAM Frame Buffer
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Memory Map
The AT91C140 memory map is divided into regions of 256 megabytes. The top memory region (0xF000_0000) is reserved and subdivided for the internal memories and shared memory and the embedded peripherals. The device can define up to five other active external memory regions by means of the static memory controller and SDRAM memory controller. The memory map is divided between both ASBs, as shown in Figure 4. All regions except the 16 megabytes between 0xFC00 0000 and 0xFCFF FFFF are located on the Main ASB. Accesses to locations between 0xFC00 0000 and 0xFCFF FFFF are routed to the MAC ASB. The memory map assumes default values on reset. External memory regions can be reprogrammed to other base addresses in the Static Memory Controller or in the SDRAM Controller. Note that the internal memory regions have fixed locations that cannot be reprogrammed. There are no hardware locks to prevent incorrect programming of the regions. Programming two or more regions to have the same base address or overlapping two memory regions results in undefined behavior. The ARM processor reset vector at address 0x00000000 is mapped into the internal ROM or external memory connected on NCE0. This selection depends on the PA0 signal pin. After booting, the ROM region can be disabled and any external memory can be mapped to the bottom of the memory map by programming SMC_CSRx or SDRAMC_ADDR. Figure 5. AT91C140 Memory Map
256M bytes 256M bytes 256M bytes 256M bytes 0x0000 0000
0x0FFF FFFF
External Static Memory connected on NCE0 External Static Memory connected on NCE1 External Static Memory connected on NCE2 External Static Memory connected on NCE3 SDRAMC
0x1000 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
SMC
0x3000 0000
0x3FFF FFFF
256M bytes
0x4000 0000 External Dynamic Memory connected on SDCS 0x4FFF FFFF
0x5000 0000
10 x 256M bytes
Unused
0xEFFF FFFF
256M bytes
0xF000 0000
0xFFFF FFFF
Internal Memories and Peripherals
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Figure 6 below shows the mapping of the internal memories and the address space reserved for the Peripheral Bridge. Figure 6. Internal Memory Mapping
Actual Size
0xFF00 0000
144M bytes
0xF8FF FFFF
Reserved 0xF900 0000
0xF9FF FFFF 0xFA00 0000
16M bytes 16M bytes
ROM Reserved
1K byte
0xFAFF FFFF 0xFB00 0000
16M bytes
0xFBFF FFFF
Reserved 0xFC00 0000 Frame Buffer Reserved
0xFDFF FFFF 0xFD00 0000
16M bytes 16M bytes 16M bytes 16M bytes
16K bytes
0xFCFF FFFF 0xFD00 0000
Reserved
0xFEFF FFFF
0xFF00 0000
0xFFFF FFFF
Peripherals
ARM ASB Arbitration
The ARM ASB is arbitrated with the following priorities: * * * The PDC has the highest priority. The Bridge from the MAC ASB has the middle priority. The ARM processor has the lowest priority.
MAC ASB Arbitration
The MAC ASB is arbitrated with the following priorities: * * * The Bridge from the ARM ASB has the highest priority. The MAC A has the middle priority. The MAC B has the lowest priority.
ASB-ASB Bridge Arbitration
The MAC ASB has two priority levels; the two MACs share low priority access and the ASB-ASB Bridge has high priority. The MACs do not burst more than four words per access and release the bus request between accesses so the MACs share a priority level with a simple round-robin arbitration scheme. The ARM is likely to be the only master accessing the MAC bus via the bridge and should not perform more than a couple of cycles before releasing the MAC bus. Care should be taken to prevent other masters on the ARM bus holding the MAC bus for more than a few cycles. Otherwise, the MACs drop frames due to FIFO overflow or underflow. When a master on one bus accesses a slave on the other bus, the following operations occur: * The local bus arbiter arbitrates the master's request for the local ASB bus if it does not already have access to the bus. * When the local bus arbiter grants the local bus to the master, the master initiates a cycle with an address corresponding to a slave on the remote bus. * The bridge is selected as the slave on the local bus and responds by inserting wait cycles. The bridge also requests the remote bus from the remote bus arbiter. 19
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* When the bridge is granted the remote bus, the two ASB buses are coupled and the transfer completes. The ASB performs pipelined arbitration. The ASB-ASB Bridge can only request the bus when the address of the slave is available. For this reason, the ASB-ASB Bridge inserts a wait cycle during the arbitration cycle on the remote bus because it cannot request the bus early.
Boot Mode
The AT91C140 has an integrated 1-Kbyte ROM to support the boot software. When the device is released from reset, the pin PA0 is sampled by the Memory Controller. If sampled low, the internal ROM becomes accessible from the address 0x0, so that the ARM processor starts execution of the Boot Program. Note that the ROM remains accessible at its normal address. If the pin PA0 is sampled high at reset, the mapping does not change and the external memory connected on NCE0 should contain a valid boot sequence. The level of the pin PA0 at resets is indicated by the RM flag in the System Mode Register (SYS_MD). Then, the RM bit can be written at any value to map to or remove the ROM from address 0x0. If PA0 is asserted on reset, the Boot Program in ROM is executed. The Boot Program is described in "Boot Program" on page 24. Figure 7 below shows the mapping of the ROM depending on the Boot Mode. Figure 7. ROM Mapping Depending on the Boot Mode
RM = 0 1K byte 0x0000 0000
0x0000 03FF
RM = 1
ROM
0x0000 0400
256M bytes
External Memory Connected on NCE0
External Memory Connected on NCE0
0x0FFF FFFF
Endianness
The AT91C140 Memory Controller operates in little-endian mode only. The user has to make sure that the data structures used by the ARM7TDMI, the Ethernet DMAs and the PDC are compliant with this mode of byte arrangement.
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Peripherals
The Peripheral Bridge allows access to the embedded peripheral user interfaces. It is optimized for low power consumption, as it is built without usage of any clock. However, any access on the peripheral is performed in two cycles. The AT91C140 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has 16K bytes of address space allocated in the upper part of the address space.
Peripheral Registers
All of the peripheral registers are 32-bits wide and support only aligned accesses. When a misaligned access is performed within the peripheral address space, the access is automatically performed at the lower aligned address. All undefined or unused register bits (marked "-") read 0. It is recommended to write them at 0 for software upward compatibility.
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Peripheral Memory Map
Figure 8 below gives the mapping of the peripherals integrated in the AT91C140.
Figure 8. Peripheral Memory Map
Peripheral Name 0xFF00 0000 SYSC
0xFF00 3FFF
Size
System Controller
16K bytes
0xFF00 4000 SMC
0xFF00 7FFF
Static Memory Controller
16K bytes
0xFF00 8000
0xFF00 BFFF
SDRAMC
SDRAM Controller
16K bytes
0xFF00 C000
0xFF00 FFFF
PIOA
Parallel I/O Controller A
16K bytes
0xFF01 0000
0xFF01 3FFF
PIOB
Parallel I/O Controller B
16K bytes
0xFF01 4000
0xFF01 7FFF
TC0, TC1, TC2
Timer Counter Channel 0, 1 and 2
16K bytes
0xFF01 8000
0xFF01 BFFF
UART A
Universal Asynchronous Receiver Transmitter A Universal Asynchronous Receiver Transmitter B Serial Peripheral Interface
16K bytes
0xFF01 C000
0xFF01 FFFF
UART B
16K bytes
0xFF02 0000
0xFF02 3FFF 0xFF02 4000
SPI
16K bytes
Reserved
0xFF02 FFFF
0xFF03 0000
0xFF03 3FFF
AIC
Advanced Interrupt Controller
16K bytes
0xFF03 4000
0xFF03 7FFF
MACA
Ethernet MAC A
16K bytes AIC is mapped at both addresses
0xFF03 8000
0xFF03 BFFF 0xFF03 C000
MACB Reserved
Ethernet MAC B
16K bytes
0xFFFF EFFF
0xFFFF F000
0xFFFF FFFF
AIC
Advanced Interrupt Controller
16K bytes
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Peripheral Data Controller (PDC)
PDC Overview
The AT91C140 features a six-channel Peripheral Data Controller (PDC) dedicated to the two on-chip UARTs and the SPI. One PDC channel is connected to the receiving channel and one to the transmitting channel of each UART and of the SPI. Each PDC channel operates as DMA (Direct Memory Access). The User Interface of a PDC channel is integrated in the memory space of each peripheral. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed number of bytes is transferred, an end-of-transfer signal is sent to the peripheral and is visible in the peripheral status register. This status bit might trigger an interrupt.
PDC Channel Priority
The transfer requests from the peripherals are treated in the order they happen. When several transfer requests happen in the same cycle, the following priority order is applied: * * * * * * the UART A receiver the UART A transmitter the UART B receiver the UART B transmitter the SPI receiver the SPI transmitter
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Boot Program
The AT91C140 can boot in several ways as explained below. When the ARM7TDMI processor is released from reset it basically attempts a fetch from address 0x00000000. Depending on an hardware configuration, the memory mapping can be altered and thus modify how the system boots. When the master reset is released, the pin PA0 is latched. Its state defines how the system boots. When PA0 is latched at 1, the AT91C140 is said to be configured in external boot mode. The initial state of the EBI maps the 1-Mbyte address range starting from 0x00000000 in the external device selected by NCE0. In this boot mode, NCE0 is assumed to be connected to an external memory device containing the suitable boot code. When PA0 is latched at 0, the AT91C140 is said to be configured in internal boot mode. The internal boot ROM normally located at base address 0xf9000000 is aliased at address 0x00000000. In this boot mode, the ARM Processor executes the first instructions out of the internal boot ROM. The boot mode is reflected by the RM bit in register SYS_MD. Reading RM at 0 indicates that the boot ROM is aliased at base address 0x00000000, eventually overlapping the memory layout defined by the SMC and the SDRAMC registers. Reading RM at 1 indicates that the boot ROM can be accessed only from base address 0xf9000000. Writing RM allows to select the mapping of the boot ROM under software control.
Boot Mode
Hardware Connection of the DataFlash
The internal boot software provides the AT91C140 with the capability of booting from an external serial DataFlash connected on the on-chip SPI interface as described above. When the internal boot software is used in conjunction with DataFlash, the latter must be connected to the AT91C140 as shown below in Figure 9. Figure 9. DataFlash Connection
AT91C140 NPCS0/PA22 MOSI MISO SPCK DataFlash CS SI SO CK
Internal Boot Software
The internal boot code goes through the following steps in sequence: * * * * * * * The processor enters the supervisor mode and all the interrupts are masked. A branch is executed into the ROM alias based from 0xf9000000. The ROM alias based at 0x00000000 is removed by writing the RM bit at 1. The clock is programmed at the highest frequency achievable without using the onchip PLL (i.e. the frequency of the crystal divided by 2). The on-chip SPI interface is setup to prepare for communications with DataFlash. A bunch of data is downloaded from the DataFlash. This data is expected to contain a formatted header describing the contents of the DataFlash. This header is analyzed to verify whether a DataFlash is actually present and contains valid executable code.
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* If the DataFlash is there and contains valid executable code, this code is downloaded into a location specified by the header, and an absolute branch to this code is performed. If the DataFlash is missing, or if the header is not valid, an absolute branch to address 0x00000000 is performed. A suitable memory device should be mapped at this address and contain the expected code.
*
DataFlash Header Details To ensure correct operation of the boot out of DataFlash, the DataFlash must contain a
valid header. This header contains several fields which define how the application software residing further must be handled. The structure of the DataFlash header is illustrated below in Table 6. Table 6. Header Structure
Field Address 0x00 0x04 0x08 0x0c 0x10 Note:
(1)
Field Name MAGIC DSRC DDST DSIZE ENTRY
Field Length 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes
1. The field address is respective to the DataFlash space. 0x00 corresponds to the first location of the DataFlash.
The MAGIC field contains a predefined magic number which allows identification of the suitability of the DataFlash. The value of this field must be 0x0075C221 to allow the boot routine to proceed. If another value is read, the boot code gives up the download and branches to 0x0000 0000 where the real application code is expected. The DSRC field contains the address where the code to be downloaded resides in DataFlash. This address is respective to the DataFlash address space (not the ARM Processor address space) and follows the non-linear addressing scheme defined in the documentation of the DataFlash. Note that all bits are not necessarily significant, depending on the specific DataFlash device. The DDST field contains the destination address where the downloaded code will be copied. This address is respective to the ARM Processor address space. Typically, this address should point into some internal RAM. The DSIZE field contains the number of bytes to be downloaded. This value is exclusive of the header. It must be even. The ENTRY field contains the address where the boot routine must branch when the download is complete. It is the entry point of the newly downloaded software. Although this is not required, the ENTRY field equals the DDST field in most cases.
Reserved Resources
The internal boot code needs some resources to operate correctly, especially as it programs some on-chip peripherals. These must not be assumed to be in their reset state when the control is given to the application code. The concerned peripherals are: * * * * the clock management system the SPI interface the PIO pin PA22 the RM bit
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The internal boot code also uses some internal RAM locations to store temporary data. These reside in the first 64 bytes of RAM, i.e. from 0xFD00 FFC0 to 0xFD00 FFFF. The DDST, DSIZE fields of the DataFlash header must not define a memory area overlapping the locations used by the internal boot routine. The ENTRY field must not point into this area.
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External Bus Interface (EBI)
The External Bus Interface (EBI) generates the signals that control access to external memories or peripheral devices. It contains two controllers, the SDRAM Controller and the Static Memory Controller and manages the sharing of data and address busses between both of these controllers.
Signal Multiplexing
Table 7. Signal Description and Multiplexing
Name [D31:0] [A9:0] A10 SDA10 [A12:11] [A18:13] A19/BA0 A20/BA1 [A23:21] SDCK SDCS RAS CAS WE DQM0-DQM3 NCE0-NCE3 NWE0-NWE3 NWR NSOE Description Data Bus Address Lines 0 to 9 Address Line 10 SDRAM Controller Address Line 10 Address Lines 11 to 12 Address Lines 13 to 18 Address Line 19 or Bank Address 0 Address Line 20 or Bank Address 1 Address Lines 21 to 23 SDRAM Clock SDRAM Controller Chip Select SDRAM Row Signal SDRAM Column Signal SDRAM Write Enable SDRAM Data Mask Enable Signals Active low chip enable Active low byte select/write strobe signals Active low write strobe signals Active low read enable signal NCE0-NCE3 NWE0-NWE3 NWR NSOE [A12:11] [A18:13] A19 A20 [A23:21] SDCK SDCS RAS CAS WE DQM0-DQM3 BA0 BA1 Controlled by SMC [D31:0] [A9:0] A10 A10 [A12:11] Controlled by SDRAMC [D31:0] [A9:0]
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SDRAM Controller (SDRAMC)
Description
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The maximum addressable SDRAM size is 256M bytes. The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank.
Block Diagram
Figure 10. SDRAM Controller Block Diagram
SDRAMC
SDCK Memory Controller SDRAMC Chip Select SDCS BA[1:0] RAS CAS System Controller ACLK WE DQM[3:0] A[12:11, 9:0] SDA10 D[31:0] User Interface
APB
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I/O Lines Description
Table 8. I/O Line Description
Name SDCK SDCS BA[1:0] RAS CAS WE DQM[3:0] A [12:11] SDA10 A[9:0] D[31:0] Description SDRAM Clock SDRAM Controller Chip Select Bank Select Signals Row Signal Column Signal SDRAM Write Enable Data Mask Enable Signals Address Bus Type Output Output Output Output Output Output Output Output Low High Low Low Low Low Active Level
Data Bus
I/O
Application Example
Hardware Interface Figure 11 below shows an example of an SDRAM device connection to the SDRAM Controller by using a 32-bit data bus width. Figure 12 shows an example of an SDRAM device connection by using a 16-bit data bus width. Figure 11. SDRAM Controller Connections to SDRAM Devices: 32-bit Data Bus Width
D0-D31 RAS CAS SDCK WE DQM0 DQM1 DQM2 DQM3
D0-D7
2M x 8 SDRAM
D0-D7 CS CKE CLK WE RAS CAS DQM A0-A11 BA0 BA1
D8-D15
2M x 8 SDRAM
D0-D7 CS CKE CLK WE RAS CAS DQM A0-A11 BA0 BA1
VDD WE
VDD WE
A0-A11 BA0 BA1
A0-A11 BA0 BA1
DQM0
DQM1
A0-A9, SDA10, A11 A19/BA0 A20/BA1
A0-A11
D16-D23 SDCS VDD WE
D0-D7 CS CKE CLK WE RAS CAS DQM
2M x 8 SDRAM
A0-A11 BA0 BA1
D24-D31
2M x 8 SDRAM
D0-D7 CS CKE CLK WE RAS CAS DQM
VDD WE
A0-A11 BA0 BA1
A0-A11 A0-A11 BA0 BA1 BA0 BA1
SDRAM Controller
DQM2
DQM3
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Figure 12. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
D0-D31 RAS CAS SDCK WE DQM0 DQM1
D0-D7
2M x 8 SDRAM
D0-D7
D8-D15
2M x 8 SDRAM
D0-D7
CS VDD CKE CLK SDWE WE RAS CAS DQM DQM0
A0--A11 BA0 BA1
A0-A11 BA0 BA1
CS VDD CKE CLK SDWE WE RAS CAS DQM DQM1
A0-A11 BA0 BA1
A0- A11 BA0 BA1
A0-A11 A0-A9, SDA10, A11 A19/BA0 A20/BA1
SDRAM Controller
SDCS
Software Interface
The SDRAM Controller's function is to make the SDRAM device access protocol transparent to the user. Table 9 to Table 13 illustrate the SDRAM device memory mapping therefore seen by the user in correlation with the device structure. Various configurations are illustrated.
32-bit Memory Data Bus Width Table 9. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Bk[1:0]
Row[10:0] Row[10:0]
Column[7:0] Column[8:0]
M[1:0] M[1:0]
Table 10. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0]
Row[11:0]
Column[7:0]
M[1:0]
16-bit Memory Data Bus Width Table 11. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M0 M0 M0
Bk[1:0] Bk[1:0] Bk[1:0]
Row[10:0] Row[10:0] Row[10:0]
Column[7:0] Column[8:0] Column[9:0]
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Table 12. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M0 M0
Bk[1:0] Bk[1:0]
Row[11:0] Row[11:0]
Column[7:0] Column[8:0]
Table 13. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M0
Bk[1:0]
Row[12:0]
Column[7:0]
SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. A minimum pause of 200 s is provided to precede any signal toggle. 2. An All Banks Precharge command is issued to the SDRAM devices. 3. Eight auto-refresh (CBR) cycles are provided. 4. A mode register set (MRS) cycle is issued to program the parameters of the SDRAM devices, in particular CAS latency and burst length. 5. A Normal Mode command is provided, 3 clocks after tMRD is met. 6. Perform a dummy access in the SDRAM Memory Space to initialize the state machine. 7. Write refresh rate into the count field in the SDRAMC Refresh Timer register. (Refresh rate = delay between refresh cycles). After these six steps, the SDRAM devices are fully functional. The commands (NOP, MRS, CBR, normal mode) are generated by programming the command field in the SDRAMC Mode register.
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Figure 13. SDRAM Device Initialization Sequence
tRP SDCK tRC tMRD
A[9:0]
SDA10
A[12:11]
SDCS
RAS CAS
WE NBS Inputs Stable for 200 sec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command
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SDRAM Controller Write Cycle
The SDRAM Controller allows burst access or single access. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) commands. For a definition of these timing parameters, refer to the "SDRAMC Configuration Register" on page 39. This is described in Figure 14 below.
Figure 14. Write Burst, 32-bit SDRAM Access
tRCD = 3 SDCS
SDCK
A[12:0]
Row n
col a
col b
col c
col d
col e
col f
col g
col h
col i
col j
col k
col l
RAS
CAS
WE
D[31:0]
Dna
Dnb
Dnc
Dnd
Dne
Dnf
Dng
Dnh
Dni
Dnj
Dnk
Dnl
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SDRAM Controller Read Cycle
The SDRAM Controller allows burst access or single access. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential read access, reading to the SDRAM device is carried out. If the next access is a sequential read access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a read command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD) command, After a read command, additional wait states are generated to comply with cas latency. The SDRAM Controller supports a cas latency of two. For definition of these timing parameters, refer to "SDRAMC Configuration Register" on page 39. This is described in Figure 15 below. Figure 15. Read Burst, 32-bit SDRAM access
tRCD = 3 SDCS CAS = 2
SDCK
A[12:0]
Row n
col a
col b
col c col d col e
col f
RAS
CAS
WE D[31:0] (Input) Dna Dnb Dnc Dnd Dne Dnf
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Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD) command. This is described in Figure 16 below.
Figure 16. Read Burst with Boundary Row Access
TRP = 3 SDCS TRCD = 3 CAS = 3
SDCK Row n A[12:0] col a col b col c col d Row m col a col b col c col d col e
RAS
CAS
WE
D[31:0]
Dna
Dnb
Dnc
Dnd
Dma
Dmb
Dmc
Dmd
Dme
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SDRAM Controller Refresh Cycles
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. A timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles. When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the ARM tries to access the SDRAM, it is held until the refresh cycle has completed. See Figure 17 below.
Figure 17. Refresh Cycle Followed by a Read Access
tRP = 3 SDCS
tRC = 8
tRCD = 3
CAS = 2
SDCK Row n Col c Col d
A[12:0]
Row m
Col a
RAS
CAS
WE D[31:0] (input)
Dnb
Dnc Dnd
Dma
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SDRAM User Interface
Base Address: 0xFF00 8000 Table 14. SDRAM Controller Register Mapping
Offset 0x00 0x04 0x08 0x0C 0x10 Register Name SDRAMC_MR SDRAMC_TR SDRAMC_CR SDRAM_16BIT SDRAMC_ADDR Register Description SDRAMC Mode Register SDRAMC Refresh Timer Register SDRAMC Configuration Register SDRAM 16-bit configuration Base address for SDCS Access Read/Write Read/Write Read/Write Read/Write Read/Write Reset State 0x00000000 0x00000800 0x0299C140 0x00000001 0x00000040
SDRAMC Mode Register
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 MODE
SDRAMC_MR Read/Write 0x00000010
30 - 22 - 14 - 6 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 MODE 0 -
* MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
MODE 0 0 0 0 0 0 1 1 0 1 0 1 Description Normal mode. Any access to the SDRAM is decoded normally. The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. The address offset with respect to the SDRAM device base address is used to program the Mode Register. For instance, when this mode is activated, an access to the "SDRAM_Base + offset" address generates a "Load Mode Register" command with the value "offset" written to the SDRAM device Mode Register. The SDRAM Controller issues a "Refresh" Command when the SDRAM device is accessed regardless of the cycle. Prior to this, an "All Banks Precharge" command must be issued. Reserved
1
0 Others
0
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SDRAMC Refresh Timer Register
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7
SDRAMC_TR Read/Write 0x00000800
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 COUNT 27 - 19 - 11 26 - 18 - 10 COUNT 3 2 1 0 25 - 17 - 9 24 - 16 - 8
* COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate of the SDRAM device and the refresh burst length where 15.6 s per row is a typical value for a burst of one length. To refresh the SDRAM device even if the reset value is not equal to 0, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out.
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SDRAMC Configuration Register
Register Name: Access Type: Reset Value:
31 - 23 TRAS 15 TRP 7 TWR
SDRAMC_CR Read/Write
0x0299C140 30 - 22 29 - 21 TRCD 14 13 TRC 6 1 5
0
28 - 20
27 - 19
26
25 TRAS 17 TRP 9 TWR 1 NC
24
18
16
12
11
10
8
4 NB
3 NR
2
0
* NC: Number of Column Bits Reset value is 8 column bits.
NC 0 0 1 1 0 1 0 1 Column Bits 8 9 10 11
* NR: Number of Row Bits Reset value is 11 row bits.
NR 0 0 1 1 0 1 0 1 Row Bits 11 12 13 Reserved
* NB: Number of Banks Reset value is two banks.
NB 0 1 Number of Banks 2 4
* TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 2 and 15. If TWR is less than or equal to 2, two clock periods are inserted by default.
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* TRC: Row Cycle Delay Reset value is eight cycles. This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 2 and 15. If TRC is less than or equal to 2, two clock periods are inserted by default. * TRP: Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 2 and 15. If TRP is less than or equal to 2, two clock periods are inserted by default. * TRCD: Row to Column Delay Reset value is three cycles. This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 2 and 15. If TRCD is less than or equal to 2, two clock periods are inserted by default. * TRAS: Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 2 and 15. If TRAS is less than or equal to 2, two clock periods are inserted by default.
SDRAMC Address Register
Register Name: SDRAMC_ADDR Access Type: Read/Write
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 SDCS_ADDR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* SDCS_ADDR This field defines the eight most significant bits of the base address of the SDRAMC.
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Static Memory Controller (SMC)
The AT91C140 features a Static Memory Controller (SMC), that enables interfacing with a wide range of external static memory on peripheral devices, including Flash, ROM, static RAM, and parallel peripherals. The SMC provides a glueless memory interface to external memory using common address, data bus and dedicated control signals. The SMC is highly programmable and has up to 24 bits of address bus, a 32- or 16-bit data bus and up to four chip select lines. The SMC supports different access protocols allowing single clock-cycle accesses. The SMC is programmed as an internal peripheral that has a standard APB bus interface and a set of memory-mapped registers. It shares the external address and data buses with the SDRAMC and any external bus master.
External Memory Mapping
The memory map associates the internal 32-bit address space with the external 24-bit address bus. The memory map is defined by programming the base address and page size of the external memories. Note that address bits A2 to A23 are significant for 32-bit memories whereas address bits A1 to A23 are significant for 16-bit memories. If the physical memory-mapped device is smaller than the programmed page size, it wraps around and appears to be repeated within the page. The SMC correctly handles any valid access to the memory device within the page. In the event of an access request to an address outside any programmed page, an abort signal is generated by the internal decoder. Two types of abort are possible: instruction prefetch abort and data abort. The corresponding exception vector addresses are 0x0000000C and 0x00000010. It is up to the system programmer to program the exception handling routine used in case of an abort. Table 15 below lists the pins used by the SMC to control external memories. Table 15. SMC Pin Description
FPDRAM [A23:0] [D31:0] NCE0-NCE3 NWE0-NWE3 NWR NSOE Description Address bus Data bus Active low chip enable Active low byte select/write strobe signals Active low write strobe signals Active low read enable signal Type Output I/O Output Output Output Output
Pin Description
Data Bus Width
A data bus width of 32 or 16 bits can be selected for each chip select. This option is controlled by the DBW field in the Chip Select Register (SMC_CSR) of the corresponding chip select. The AT91C140 boots up with a data bus as defined by the DBW32 pin. If tied high, Chip Select 0 is automatically setup to be 32-bit wide. If tied low, the Chip Select 0 is configured to be 16-bit wide. The DBW bit in SMC_CSR resets accordingly to the level of DBW32.
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Byte Write or Byte Select Each chip select can be individually programmed to operate in Byte Write or Byte Select Mode. Mode
* * The Byte Write Mode supports four (32-bit bus) or two (16-bit bus) byte writes and a single read signal. The Byte Select Mode selects the appropriate byte(s) using four (32-bit bus) or two (16-bit bus) byte-select lines and separate read and write signals.
This option is controlled by the BAT bit in the Chip Select Register (SMC_CSR0 to SMC_CSR3). The Byte Write Mode is used to connect four 8-bit devices on a 32-bit bus or two 8-bit devices on a 16-bit bus. For a 32-bit bus: * The NWE0 signal is used as the write enable signal for byte 0. * The NWE1 signal is used as the write enable signal for byte 1. * The NWE2 signal is used as the write enable signal for byte 2. * The NWE3 signal is used as the write enable signal for byte 3. * The NSOE signal enables memory reads to all memory blocks. For a 16-bit bus: * The NWE0 signal is used as the write enable signal for byte 0. * The NWE1 signal is used as the write enable signal for byte 1. * The NSOE signal enables memory reads to all memory blocks. The Byte Select Mode is used to connect one 32-bit device or two 16-bit devices on a 32-bit data bus or one 16-bit device on a 16-bit data bus. For a 32-bit bus: * The NWE0 signal is used to select byte 0 for read and write operations. * The NWE1 signal is used to select byte 1 for read and write operations. * The NWE2 signal is used to select byte 2 for read and write operations. * The NWE3 signal is used to select byte 3 for read and write operations. * The NWR signal is used as the write enable signal for the memory block. * The NSOE signal enables memory reads to the memory block. For a 16-bit bus: * The NWE0 signal is used to select byte 0 for read and write operations. * The NWE1 signal is used to select byte 1 for read and write operations. * The NWR signal is used as the write enable signal for the memory block. * The NSOE signal enables memory reads to the memory block.
Read Protocols
The SMC provides two alternative protocols for external memory read access; standard and early read. The difference between the two protocols lies in the timing of the NSOE (read cycle) waveform. The protocol is selected by the DRP field in the Memory Control Register (SMC_MCR) and is valid for all memory devices. Standard read protocol is the default protocol after reset.
Standard Read Protocol
Standard read protocol implements a read cycle in which NSOE and the write strobes are similar. Both are active during the second half of the clock cycle. The first half of the clock cycle allows time to ensure completion of the previous access, as well as the output of address and NCE before the read cycle begins.
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During a standard read protocol external memory access, the chip enable signal sNCE0 to NCE3 are set low and the address lines are valid at the beginning of the access, whereas NSOE goes low only in the second half of the master clock cycle to avoid bus conflict. The write strobes are the same in both protocols. The write strobes always go low in the second half of the master clock cycle. Early Read Protocol Early read protocol provides more time for a read access from the memory by asserting NSOE at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NSOE remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol allows a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contention on the external bus. In early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is generated in addition to any other programmed wait states (i.e., data float wait). No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. During a write cycle, the data becomes valid after the falling edge of the write strobe signal and remains valid after the rising edge of the write strobe. The external write strobe waveform on the appropriate write strobe pin is used to control the output data timing to guarantee this operation. Thus, it is necessary to avoid excessive loading of the write strobe pins, which could delay the write signal too long and cause a contention with a subsequent read cycle in standard protocol. In early read protocol, the data can remain valid longer than in standard read protocol due to the additional wait cycle that follows a write access. The SMC can automatically insert wait states. The different types of wait states are: * Standard wait states * Data float wait states * Chip select change wait states * Early read wait states, as described in "Early Read Protocol" above. Standard Wait States Each chip select can be programmed to insert one or more wait states during an access on the corresponding device. This is done by setting the WSE field in the corresponding SMC_CSR. The number of cycles to insert is programmed in the NWS field in the same register. When no wait state is programmed (WSE = 0), the NWE signal lasts only one-half cycle. If at least one wait state is programmed, the NWE signal lasts an integer number of cycles, accordingly to the number of wait states programmed. Some memory devices are slow to release the external bus. For such devices it is necessary to add wait states (data float waits) after a read access before starting a write access or a read access to a different external memory. The Data Float Output Time (TDF) for each external memory device is programmed in the TDF field of the SMC_CSR register for the corresponding chip select. The value (0 7 clock cycles) indicates the number of data float waits to be inserted and represents the time allowed for the data output to go to high impedance after the memory is disabled. The SMC keeps track of the programmed external data float time even when it makes internal accesses to ensure that the external memory system is not accessed while it is still busy. 43
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Write Protocol
Wait States
Data Float Wait States
Internal memory accesses and consecutive accesses to the same external memory do not insert added data float wait states. When data float wait states are being used, the SMC prevents the SDRAM Controller from accessing the external data bus. Chip Select Change Wait States A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no wait states have already been inserted). If any wait states have already been inserted (e.g., data float wait), then none are added. Figure 18 on page 45 shows a write to memory 0 followed by a write and a read to memory 1. SMC_CSR0 is programmed for one wait state with BAT = 0 and TDF = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and TDF = 0. Early Read Protocol is enabled. The write to memory 0 is a word access and therefore all four NWE strobes are active. As BAT = 0, they are configured as write strobes and have the same timing as NWR. As the access employs a single wait state, the write strobe pulse is one clock cycle long. There is a chip select change wait state between the memory 0 write and the memory 1 write. The new address is output at the end of the memory 0 access, but the strobes are delayed for one clock cycle. The write to memory 1 is a half-word access to an odd half-word address and, therefore, NWE2 and NWE3 are active. As BAT = 1, they are configured as byte select signals and have the same timing as NCE. As the access has no internal wait states, the write strobe pulse is one- half clock cycle long. Data and address are driven until the write strobe rising edge is sensed at the AT91C140 pin to guarantee positive hold times. There is an early read wait state between memory 1 write and memory 1 read to provide time for the AT91C140 to disable the output data before the memory is read. If the read was normal mode, i.e., not early, the NSOE strobe would not fall until the rising edge of ACLK and no wait state would be inserted. If the write and early read were to different memories, then the early read wait state is not required as a chip select wait state will be implemented. The read from memory 1 is a byte access to an address with a byte offset of 2 and therefore only NWE2 is active.
Signal Waveforms
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Figure 18. Write to Memory 0, Write and Read to Memory 1
Internal Wait State Chip Select Wait State Early Read Wait State
ACLK
NCE0
NCE1
A
NWR NSOE
NWE0
NWE1
NWE2
NWE3
D out D in
Figure 19 on page 46 shows a write and a read to memory 0 followed by a read and a write to memory 1. SMC_CSR0 is programmed for zero wait states with BAT = 0 and DFT = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and DFT = 1. SMC_MCR is programmed for normal reads from all memories. The write to memory 0 is a byte access and, therefore, only one NWE strobe is active. As BAT = 0, they are configured as write strobes and have the same timing as NWR. The memory 0 read immediately follows the write as early reads are not configured and an early read wait state is not required. As early reads are not configured, the read strobe pulse is one-half clock cycle long. There is a chip select change wait state between the memory 0 write and the memory 1 read. The new address is output at the end of the memory 0 access but the strobes are delayed for one clock cycle. The write to memory 1 is a half-word access to an odd half-word address and, therefore, NWE2 and NWE3 are active. As BAT = 1, they are configured as byte select signals and have the same timing as NCE. As DFT = 1 for memory 1, a wait state is implemented between the read and write to provide time for the memory to stop driving the data bus. DFT wait states are only implemented at the end of read accesses.
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The read from memory 1 is a byte access to an address with a byte offset of 2 and, therefore, only NWE2 is active. Figure 19. Write and Read to Memory 0, Read and Write to Memory 1
Chip Select Wait State ACLK Data Float Wait State
NCE0
NCE1
A
NWR NSOE
NWE0
NWE1 NWE2
NWE3
D out D in
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SMC User Interface
The memory control register (SMC_MCR) is used to program the number of active chip selects and data read protocol. Four chip select registers (SMC_CSR0 to SMC_CSR3) are used to program the parameters for the individual external memories. Each SMC_CSR must be programmed with a different base address, even for unused chip selects. The SMC_CSR register resets according to the DBW32 pin. During the boot sequence, the Chip Select Registers must be programmed as required depending on the devices connected on the external bus. The chip select addresses that are programmed take effect immediately. Wait states also take effect immediately when they are programmed to optimize boot program execution. Table 16. SMC Register Mapping
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 Register Name SMC_CSR0 SMC_CSR1 SMC_CSR2 SMC_CSR3 - - - - - SMC_MCR Register Description Chip Select Register Chip Select Register Chip Select Register Chip Select Register Reserved Reserved Reserved Reserved Reserved Memory Control Register Access Read/Write Read/Write Read/Write Read/Write - - - - - Read/ Write Reset Value 0x0000203D 0x0000203E 0x10000000 0x20000000 0x30000000 - - - - - 0x0
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SMC Chip Select Register
Register Name: Access:
31
SMC_CSR0..SMC_CSR3 Read/Write
30 29 28 BA 27 26 25 24
23
22 BA
21
20
19 - 11
18 - 10 TDF 2
17 - 9
16 - 8 PAGES 0 DBW
15 - 7 PAGES
14 - 6 MWS
13 CSEN 5 WSE
12 BAT 4
3 NWS
1
* DBW: Data Bus Width
DBW 0 0 1 1 0 1 0 1 Data Bus Width Reserved 16-bit external bus 32-bit external bus Reserved
* NWS: Number of Wait States * WSE: Wait State Enable * MWS: Multiply Wait States
NWS X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 WSE MWS = 0 0 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 Wait States Number MWS = 1 0 8 16 24 32 40 48 56 64
* PAGES: Page Size
PAGES 0 0 1 1 0 1 0 1 Page Size 1M byte 4M bytes 16M bytes Reserved Base Address BA20-BA31 BA22-BA31 BA24-BA31 -
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* TDF: Data Float Output Time
TDF 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Cycles after Transfer 0 1 2 3 4 5 6 7
* BAT: Byte Access Mode 0 = Byte Write Mode 1= Byte Select Mode * CSEN: Chip Select Enable 0 = Chip Select is disabled 1 = Chip Select is enabled * BA: Base Address This field contains the high-order bits of the base address. If the page size is larger than 1M byte, then the unused bits of the base address are ignored by the SMC decoder.
SMC Memory Control Register
Register Name: Access Type:
31 - 23 - 15 - 7 -
SMC_MCR Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 DRP 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 -
* DRP: Data Read Protocol 0 =Standard Read Mode 1 =Early Read Mode
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Ethernet MAC (EMAC)
The AT91C140 features two identical Ethernet MACs, both of which feature the following: * * * * * * * * * * * * Compatible with IEEE Standard 802.3 10 and 100 Mbits per Second Data Throughput Capability Full- and Half-duplex Operation Media Independent Interface to the Physical Layer Register Interface to Address, Status and Control Registers DMA Interface Interrupt Generation to Signal Receive and Transmit Completion 28-byte Transmit and 28-byte Receive FIFOs Automatic Pad and CRC Generation on Transmitted Frames Address Checking Logic to Recognize Four 48-bit Addresses Supports Promiscuous Mode Where All Valid Frames are Copied to Memory Supports Physical Layer Management through MDIO Interface
The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model between the physical layer (PHY) and the logical link layer (LLC). It controls the data exchange between a host and a PHY layer according to Ethernet IEEE 802.3 data frame format. The Ethernet MAC contains the required logic and transmit and receive FIFOs for DMA management. In addition, it is interfaced through MDIO/MDC pins for PHY layer management. The Ethernet MAC transfers data in media-independent interface (MII).
Block Diagram
Figure 20. Block Diagram
MAC ASB DMA Mx_TXCLK, Mx_RXCLK Mx_TXEN, Mx_TXER APB Bridge Mx_CRS, Mx_COL Mx_RXER, Mx_RXDV
APB
Ethernet MAC
Mx_RXD[3:0] Mx_TXD[3:0] Mx_MDC ACLK Interrupt Control Mx_MDIO
EMAC IRQ
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Media Independent Interface
Table 17. Pin Configuration
MII Signal Transmit Clock Carrier Sense Collision Detect Receive Data Valid 4-bit Receive Data Receive Error Receive Clock Transmit Enable 4-bit Transmit Data Transmit Error Signal Name ETXCK ECRS ECOL ERXDV ERX0-ERX3 ERXER ERXCK ETXEN ETX0-ETX3 ETXER Pin Name EMAC A MA_TXCLK MA_CRS MA_COL MA_RXDV MA_RXD[0:3] MA_RXER MA_RXCLK MA_TXEN MA_TXD[0:3] MA_TXER Pin Name EMAC B MB_TXCLK MB_CRS MB_COL MB_RXDV MB_RXD[0:3] MB_RXER MB_RXCLK MB_TXEN MB_TXD[0:3] MB_TXER
Transmit/Receive Operation
Table 18. Packet Format
Preamble Alternating 1s/0s Up to 7 bytes Note: SFD 1 byte
A standard IEEE 802.3 packet consists of the following fields: preamble, start of frame delimiter (SFD), destination address (DA), source address (SA), length, data (Logical Link Control Data) and frame check sequence CRC32 (FCS).
Frame(1) DA 6 bytes SA 6 bytes Length/type 2 bytes LLC Data PAD FCS 4 bytes
1. Frame Length between 64 bytes and 1518 bytes.
The packets are Manchester-encoded and -decoded and transferred serially using NRZ data with a clock. All fields are of fixed length except for the data field. The MAC generates and appends the preamble, SFD and CRC fields during transmission. The preamble and SFD fields are stripped during reception. Preamble and Start of Frame Delimiter (SFD) The preamble field is used to acquire bit synchronization with an incoming packet. When transmitted, each packet contains 62 bits of alternating 1,0 preamble. Some of this preamble is lost as the packet travels through the network. Byte alignment is performed with the Start of Frame Delimiter (SFD) pattern that consists of two consecutive 1's. The destination address (DA) indicates the destination of the packet on the network and is used to filter unwanted packets. There are three types of address formats: physical, multicast and broadcast. The physical address is a unique address that corresponds only to a single node. All physical addresses have an MSB of 0. Multicast addresses begin with an MSB of 1. The MAC filters multicast addresses using a standard hashing algorithm that maps all multicast addresses into a 6-bit value. This 6-bit value indexes a 64-bit array that filters the value. If the address consists of all ones, it is a broadcast address, indicating that the packet is intended for all nodes. Source Address (SA) The source address (SA) is the physical address of the node that sent the packet. Source addresses cannot be multicast or broadcast addresses. This field is passed to buffer memory.
Destination Address (DA)
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Length/Type
If the value of this field is less than or equal to 1500, then the Length/Type field indicates the number of bytes in the subsequent LLC Data field. If the value of this field is greater than or equal to 1536, then the Length/Type field indicates the nature of the MAC client protocol (protocol type). The data field consists of anywhere from 46 to 1500 bytes. Messages longer than 1500 bytes need to be broken into multiple packets. Messages shorter than 46 bytes require appending a pad to bring the data field to the minimum length of 46 bytes. If the data field is padded, the number of valid data bytes is indicated in the length field. The Frame Check Sequence (FCS) is a 32-bit CRC field, calculated and appended to a packet during transmission to allow detection of errors when a packet is received. During reception, error free packets result in a specific pattern in the CRC generator. Packets with improper CRC will be rejected. The original Ethernet standards define the minimum frame size as 64 bytes and the maximum as 1518 bytes. These numbers include all bytes from the Destination MAC Address field through the Frame Check Sequence field. The Preamble and Start Frame Delimiter fields are not included when quoting the size of a frame. The IEEE 802.3ac standard extended the maximum allowable frame size to 1522 bytes to allow a VLAN tag to be inserted into the Ethernet frame format. The BIG bit defined in the ETH_CFG register processes packets with a VLAN tag. The VLAN protocol permits insertion of an identifier, or tag, into the Ethernet frame format to identify the VLAN to which the frame belongs. It allows frames from stations to be assigned to logical groups. This provides various benefits, such as easing network administration, allowing formation of work groups, enhancing network security, and providing a means of limiting broadcast domains (refer to IEEE standard 802.1Q for definition of the VLAN protocol). The 802.3ac standard defines only the implementation details of the VLAN protocol that are specific to Ethernet. If present, the 4-byte VLAN tag is inserted into the Ethernet frame between the Source MAC Address field and the Length field. The first 2 bytes of the VLAN tag consist of the "802.1Q Tag Type" and are always set to a value of 0x8100. The 0x8100 value is a reserved Length/Type field assignment that indicates the presence of the VLAN tag, and signals that the traditional Length/Type field can be found at an offset of four bytes further into the frame. The last two bytes of the VLAN tag contain the following information. * * * The first three bits are a User Priority Field that may be used to assign a priority level to the Ethernet frame. The following one bit is a Canonical Format Indicator (CFI) used in Ethernet frames to indicate the presence of a Routing Information Field (RIF). The last twelve bits are the VLAN Identifier (VID) that uniquely identifies the VLAN to which the Ethernet frame belongs.
LLC Data
Frame Check Sequence Field (FCS)
Frame Format Extensions
With the addition of VLAN tagging, the 802.3ac standard permits the maximum length of an Ethernet frame to be extended from 1518 bytes to 1522 bytes. Table 19 on page 53 illustrates the format of an Ethernet frame that has been "tagged" with a VLAN identifier according to the IEEE 802.3ac standard.
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Table 19. Ethernet Frame with VLAN Tagging
Preamble Start Frame Delimiter Dest. MAC Address Source MAC Address Length/Type = 802.1Q Tag Type Tag Control Information Length / Type MAC Client Data Pad Frame Check Sequence 7 bytes 1 byte 6 bytes 6 bytes 2 byte 2 bytes 2 bytes 0 - n bytes 0 - p bytes 4 bytes
DMA Operations
Frame data is transferred to and from the Ethernet MAC via the DMA interface. All transfers are 32-bit words and may be single accesses or bursts of two, three or four words. Burst accesses do not cross 16-byte boundaries. The DMA controller performs four types of operations on the ASB bus. In order of priority, these operations are receive buffer manager read, receive buffer manager write, transmit data DMA read and receive data DMA write.
Transmitter Mode
Transmit frame data needs to be stored in contiguous memory locations. It does not need to be word-aligned. The transmit address register is written with the address of the first byte to be transmitted. Transmit is initiated by writing the number of bytes to transfer (length) to the transmit control register. The transmit channel then reads data from memory 32 bits at a time and places them in the transmit FIFO. The transmit block starts frame transmission when three words have been loaded into the FIFO. The transmit address register must be written before the transmit control register. While a frame is being transmitted, it is possible to set up one other frame for transmission by writing new values to the transmit address and control registers. Reading the transmit address register returns the address of the buffer currently being accessed by the transmit FIFO. Reading the transmit control register returns the total number of bytes to be transmitted. The BNQ bit in the Transmit Status Register indicates whether another buffer can be safely queued. An interrupt is generated whenever this bit is set. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO word-by-word. If necessary, padding is added to make the frame length 60 bytes. The CRC is calculated as a 32-bit polynomial. This is inverted and appended to the end of the frame, making the frame length a minimum of 64 bytes. The CRC is not appended if the NCRC bit is set in the transmit control register. In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the inter-frame gap.
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In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to deassert and then starts transmission after the inter-frame gap of 96 bit-times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retries transmission after the backoff time has elapsed. An error is indicated and any further attempts aborted if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion. Underrun also causes TXER to be asserted. Receiver Mode When a packet is received, it is checked for valid preamble, CRC, alignment, length and address. If all these criteria are met, the packet is stored successfully in a receive buffer. If at the end of reception the CRC is bad, then the received buffer is recovered. Each received frame including CRC is written to a single receive buffer. Receive buffers are word-aligned and are capable of containing 1518 or 1522 bytes (BIG = 1 in ETH_CFG) of data (the maximum length of an Ethernet frame). The start location for each received frame is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. Each entry in the list consists of two words. The first word is the address of the received buffer; the second is the receive status. Table 20 defines an entry in the received buffer descriptor list. To receive frames, the buffer queue must be initialized by writing an appropriate address to bits [31:2] in the first word of each list entry. Bit zero of word zero must be written with zero. After a frame is received, bit zero becomes set and the second word indicates what caused the frame to be copied to memory. The start location of the received buffer descriptor list should be written to the received buffer queue pointer register before receive is enabled (by setting the receive enable bit in the network control register). As soon as the received block starts writing received frame data to the receive FIFO, the received buffer manager reads the first receive buffer location pointed to by the received buffer queue pointer register. If the filter block is active, the frame should be copied to memory; the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. If the frame is received without error, the queue entry is updated. The buffer pointer is rewritten to memory with its low-order bit set to indicate successful frame reception and a used buffer. The next word is written with the length of the frame and how the destination address was recognized. The next receive buffer location is then read from the following word or, if the current buffer pointer had its wrap bit set, the beginning of the table. The maximum number of buffer pointers before a wrap bit is seen is 1024. If a wrap bit is not seen by then, a wrap bit is assumed in that entry. The received buffer queue pointer register must be written with zero in its lowerorder bit positions to enable the wrap function to work correctly. If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer unavailable bit in the received status register and triggers an interrupt. The frame is discarded and the queue entry is reread on reception of the next frame to see if the buffer is now available. Each discarded frame increments a statistics register that is cleared on being read. When there is network congestion, it is possible for the MAC to be programmed to apply back pressure. This is when half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (a default pattern). 54
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Reading the received buffer queue register returns the location of the queue entry currently being accessed. The queue wraps around to the start after either 1024 entries (i.e., 2048 words) or when the wrap bit is found to be set in bit 1 of the first word of an entry. Table 20. Received Buffer Descriptor List
Bit Word 0 31:2 1 Base address of receive buffer Wrap bit. If this bit is set, the counter that is ORed with the received buffer queue pointer register to give the pointer to entries in this table is cleared after the buffer is used. Ownership bit. 1 indicates software owns the pointer, 0 indicates that the DMA owns the buffer. If this bit is not zero when the entry is read by the receiver, the buffer unavailable bit is set in the received status register and the receiver goes inactive. Function
0
Word 1 31 30 29 28 27 26 25 24 23 22:11 10:0 Global all ones broadcast address detected Multicast hash match Unicast hash match External address Unknown source address (reserved for future use) Local address match (Specific address 1 match) Local address match (Specific address 2 match) Local address match (Specific address 3 match) Local address match (Specific address 4 match) Reserved; written to 0 Length of frame including FCS
Address Checking
Whether or not a frame is stored depends on what is enabled in the network configuration register, the contents of the specific address and hash registers and the frame destination address. In this implementation of the MAC the frame source address is not checked. A frame is not copied to memory if the MAC is transmitting in half-duplex mode at the time a destination address is received. The hash register is 64 bits long and takes up two locations in the memory map. There are four 48-bit specific address registers, each taking up two memory locations. The first location contains the first four bytes of the address; the second location contains the last two bytes of the address stored in its least significant byte positions. The addresses stored can be specific, group, local or universal. Ethernet frames are transmitted a byte at a time, LSB first. The first bit (i.e., the LSB of the first byte) of the destination address is the group/individual bit and is set one for multicast addresses and zero for unicast. This bit corresponds to bit 24 of the first word of
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the specific address register. The MSB of the first byte of the destination address corresponds to bit 31 of the specific address register. The specific address registers are compared to the destination address of received frames once they have been activated. Addresses are deactivated at reset or when the first byte [47:40] is written and activated or when the last byte [7:0] is written. If a receive frame address matches an active address, the local match signal is set and the store frame pulse signal is sent to the DMA block via the ACLK synchronization block. A frame can also be copied if a unicast or multicast hash match occurs, it has the broadcast address of all ones, or the copy all frames bit in the network configuration register is set. The broadcast address of 0xFFFFFFFF is recognized if the no broadcast bit in the network configuration register is zero. This sets the broadcast match signal and triggers the store frame signal. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. So all multicast frames can be received by setting all bits in the hash register. The CRC algorithm reduces the destination address to a 6-bit index into a 64-bit hash register.If the equivalent bit in the register is set, the frame is matched depending on whether the frame is multicast or unicast and the appropriate match signals are sent to the DMA block. If the copy all frames bit is set in the network configuration register, the store frame pulse is always sent to the DMA block as soon as any destination address is received.
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EMAC User Interface
MACA Memory Address: 0xFF034000 MACB Memory Address: 0xFF038000 Table 21. Ethernet MAC Register Mapping
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 Note: Register Name ETH_CTL ETH_CFG ETH_SR ETH_TAR ETH_TCR ETH_TSR ETH_RBQP - ETH_RSR ETH_ISR ETH_IER ETH_IDR ETH_IMR ETH_MAN ETH_FRA ETH_SCOL ETH_MCOL ETH_OK ETH_SEQE ETH_ALE ETH_DTE ETH_LCOL ETH_ECOL ETH_CSE ETH_TUE ETH_CDE ETH_ELR ETH_RJB ETH_USF ETH_SQEE ETH_DRFC ETH_HSH ETH_HSL ETH_SA1L ETH_SA1H ETH_SA2L ETH_SA2H ETH_SA3L ETH_SA3H ETH_SA4L ETH_SA4H Register Description Network Control Register Network Configuration Register Network Status Register Transmit Address Register Transmit Control Register Transmit Status Register Receive Buffer Queue Pointer Reserved Receive Status Register Interrupt Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register PHY Maintenance Register Statistics Registers(1) Frames Transmitted OK Register Single Collision Frame Register Multiple Collision Frame Register Frames Received OK Register Frame Check Sequence Error Register Alignment Error Register Deferred Transmission Frame Register Late Collision Register Excessive Collision Register Carrier Sense Error Register Transmit Underrun Error Register Code Error Register Excessive Length Error Register Receive Jabber Register Undersize Frame Register SQE Test Error Register Discarded RX Frame Register Address Registers Hash Address High [63:32] Hash Address Low [31:0] Specific Address 1 Low, First 4 Bytes Specific Address 1 High, Last 2 Bytes Specific Address 2 Low, First 4 Bytes Specific Address 2 High, Last 2 Bytes Specific Address 3 Low, First 4 Bytes Specific Address 3 High, Last 2 Bytes Specific Address 4 Low, First 4 Bytes Specific Address 4 High, Last 2 Bytes Read/Write Read/Write Read/Write Read-only Read/Write Read/Write Read/Write Read/Write Read-only Read/Write Read/Write Write-only Write-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset 0x0 0x800 0x6 0x0 0x0 0x18 0x0 0x0 0x0 0x0 - - 0xFFF 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
1. For further details on the statistics registers, see Table 22, "Statistics Register Block," on page 71.
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EMAC Control Register
Register Name: Access Type:
31
ETH_CTL Read/Write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
BP
0
WES
ISR
CSR
MPE
TE
RE
LBL
LB
* LB: Loopback . When set, loopback signal is at high level. * LBL: Loopback Local When set, connects ETX[3:0] to ERX[3:0], ETXEN to ERXDV, forces full duplex and drives ERXCK and ETXCK_REFCK with ACK divided by 4. * RE: Receive Enable When set, enables the Ethernet MAC to receive data. * TE: Transmit Enable When set, enables the Ethernet transmitter to send data. * MPE: Management Port Enable Set to one to enable the management port. When zero, forces MDIO to high impedance state. * CSR: Clear Statistics Registers This bit is write-only. Writing a one clears the statistics registers. * ISR: Increment Statistics Registers This bit is write-only. Writing a one increments all the statistics registers by one for test purposes. * WES: Write Enable for Statistics Registers Setting this bit to one makes the statistics registers writable for functional test purposes. * BP: Back Pressure If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern).
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EMAC Mode Register
Name: Access Type:
31
ETH_CFG Read/Write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
RTY
4 3
CLK
2
EAE
1
BIG
0
UNI
MTI
NBC
CAF
-
BR
FD
SPD
* SPD: Speed Set to 1 to indicate 100 Mbit/sec, 0 for 10 Mbit/sec. Has no other functional effect. * FD: Full Duplex If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. * BR: Bit Rate * CAF: Copy All Frames When set to 1, all valid frames are received. * NBC: No Broadcast When set to 1, frames addressed to the broadcast address of all ones are not received. * MTI: Multicast Hash Enable When set multicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register. * UNI: Unicast Hash Enable When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register. * BIG: Receive 1522 Bytes When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length. This bit allows to receive extended Ethernet frame with "VLAN tag" (IEEE 802.3ac) * EAE: External Address Match Enable * CLK The ARM clock is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that ACK is divided by 32.
CLK 00 01 10 11 MDC ACK divided by 8 ACK divided by 16 ACK divided by 32 ACK divided by 64
* RTY: Retry Test When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation.
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EMAC Status Register
Name: Access Type:
31
ETH_SR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
IDLE
MDIO
LINK
* LINK 0 = LINK is at 0. 1 = LINK is at 1. * MDIO 0 = MDIO pin not set. 1 = MDIO pin set. * IDLE 0 = PHY logic is idle. 1 = PHY logic is running.
EMAC Transmit Address Register
Name: Access Type:
31
ETH_TAR Read/Write
30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
7 6 5 4 3 2 1 0
ADDRESS
* ADDRESS: Transmit Address Register Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the transmit FIFO. Note that if the two least significant bits are not zero, transmit starts at the byte indicated.
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EMAC Transmit Control Register
Name: Access Type:
31
ETH_TCR Read/Write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
NCRC
7
-
6
-
5
-
4
-
3 2
LEN
1 0
LEN
* LEN: Transmit Frame Length This register is written to the number of bytes to be transmitted excluding the four CRC bytes unless the no CRC bit is asserted. Writing these bits to any non-zero value initiates a transmission. If the value is greater than 1514 (1518 if no CRC is being generated), an oversize frame is transmitted. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Must always be written in address-then-length order. Reads as the total number of bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) Frame transmission does not start until two 32-bit words have been loaded into the transmit FIFO. The length must be great enough to ensure two words are loaded. * NCRC: No CRC If this bit is set, it is assumed that the CRC is included in the length being written in the low-order bits and the MAC does not append CRC to the transmitted frame. If the buffer is not at least 64 bytes long, a short frame is sent. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Reads as the value of the frame currently being transmitted.
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EMAC Transmit Status Register
Name: Access Type:
31
ETH_TSR Read/Write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UND
COMP
BNQ
IDLE
RLE
COL
OVR
* OVR: Ethernet Transmit Buffer Overrun Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when bit BNQ was not set. Cleared by writing a one to this bit. * COL: Collision Occurred Set by the assertion of a collision. Cleared by writing a one to this bit. * RLE: Retry Limit Exceeded Cleared by writing a one to this bit. * IDLE: Transmitter Idle Asserted when the transmitter has no frame to transmit. Cleared when a length is written to transmit frame length portion of the Transmit Control register. This bit is read-only. * BNQ: Ethernet Transmit Buffer not Queued Software may write a new buffer address and length to the transmit DMA controller when set. Cleared by having one frame ready to transmit and another in the process of being transmitted. This bit is read-only. * COMP: Transmit Complete Set when a frame has been transmitted. Cleared by writing a one to this bit. * UND: Transmit Underrun Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC. Cleared by writing a one to this bit.
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EMAC Receive Buffer Queue Pointer Register
Name: Access Type:
31
ETH_RBQP Read/Write
30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
7 6 5 4 3 2 1 0
ADDRESS
* ADDRESS: Receive Buffer Queue Pointer Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive buffer is forced to word alignment.
EMAC Receive Status Register
Name: Access Type:
31
ETH_RSR Read/Write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
OVR
REC
BNA
* BNA: Buffer Not Available An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit. * REC: Frame Received One or more frames have been received and placed in memory. Cleared by writing a one to this bit. * OVR: RX Overrun The DMA block was unable to store the receive frame to memory, either because the MAC ASB bus was not granted in time or because an abort occurred. The buffer is recovered if this happens. Cleared by writing a one to this bit.
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EMAC Interrupt Status Register
Name: Access Type:
31
ETH_ISR Read/Write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
ABT
3
ROVR
2
LINK
1
TIDLE
0
TCOM
TBRE
RTRY
TUND
TOVR
RBNA
RCOM
DONE
* DONE: Management Done The PHY maintenance register has completed its operation. Cleared on read. * RCOM: Receive Complete A frame has been stored in memory. Cleared on read. * RBNA: Receive Buffer Not Available Cleared on read. * TOVR: Transmit Buffer Overrun Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read. * TUND: Transmit Buffer Underrun Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read. * RTRY: Retry Limit Retry limit exceeded. Cleared on read. * TBRE: Transmit Buffer Register Empty Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read. * TCOM: Transmit Complete Set when a frame has been transmitted. Cleared on read. * TIDLE: Transmit Idle Set when all frames have been transmitted. Cleared on read. * LINK Set when LINK pin changes value. * ROVR: RX Overrun Set when the RX overrun status bit is set. Cleared on read. * ABT: Abort Set when the DMA generates an Abort. Cleared on read.
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EMAC Interrupt Enable Register
Name: Access Type:
31
ETH_IER Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
ABT
3
ROVR
2
LINK
1
TIDLE
0
TCOM
TBRE
RTRY
TUND
TOVR
RBNA
RCOM
DONE
* DONE: Management Done Interrupt Enable * RCOM: Receive Complete Interrupt Enable * RBNA: Receive Buffer Not Available Interrupt Enable * TOVR: Transmit Buffer Overrun Interrupt Enable * TUND: Transmit Buffer Underrun Interrupt Enable * RTRY: Retry Limit Interrupt Enable * TBRE: Transmit Buffer Register Empty Interrupt Enable * TCOM: Transmit Complete Interrupt Enable * TIDLE: Transmit Idle Interrupt Enable * LINK: LINK Interrupt Enable * ROVR: RX Overrun Interrupt Enable * ABT: Abort Interrupt Enable 0 =No effect. 1 =Enables the corresponding interrupt.
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EMAC Interrupt Disable Register
Name: Access Type:
31
ETH_IDR Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
ABT
3
ROVR
2
LINK
1
TIDLE
0
TCOM
TBRE
RTRY
TUND
TOVR
RBNA
RCOM
DONE
* DONE: Management Done Interrupt Disable * RCOM: Receive Complete Interrupt Disable * RBNA: Receive Buffer Not Available Interrupt Disable * TOVR: Transmit Buffer Overrun Interrupt Disable * TUND: Transmit Buffer Underrun Interrupt Disable * RTRY: Retry Limit Interrupt Disable * TBRE: Transmit Buffer Register Empty Interrupt Disable * TCOM: Transmit Complete Interrupt Disable * TIDLE: Transmit Idle Interrupt Disable * LINK: LINK Interrupt Disable * ROVR: RX Overrun Interrupt Disable * ABT: Abort Interrupt Disable 0 =No effect. 1 =Disables the corresponding interrupt.
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EMAC Interrupt Mask Register
Name: Access Type:
31
ETH_IMR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
ABT
3
ROVR
2
LINK
1
TIDLE
0
TCOM
TBRE
RTRY
TUND
TOVR
RBNA
RCOM
DONE
* DONE: Management Done Interrupt Mask * RCOM: Receive Complete Interrupt Mask * RBNA: Receive Buffer Not Available Interrupt Mask * TOVR: Transmit Buffer Overrun Interrupt Mask * TUND: Transmit Buffer Underrun Interrupt Mask * RTRY: Retry Limit Interrupt Mask * TBRE: Transmit Buffer Register Empty Interrupt Mask * TCOM: Transmit Complete Interrupt Mask * TIDLE: Transmit Idle Interrupt Mask * LINK: LINK Interrupt Mask * ROVR: RX Overrun Interrupt Mask * ABT: Abort Interrupt Mask 0 =The corresponding interrupt is enabled. 1 =The corresponding interrupt is not enabled. Important Note: The interrupt is disabled when the corresponding bit is set. This is non-standard with other peripherals of the product, as generally a mask bit set enables the interrupt.
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EMAC PHY Maintenance Register
Name: Access Type:
31
ETH_MAN Read/Write
30 29 28 27 26 25 24
LOW
23
HIGH
22 21
RW
20 19 18
PHYA
17 16
PHYA
15 14 13
REGA
12 11 10 9
CODE
8
DATA
7 6 5 4 3 2 1 0
DATA
Writing to this register starts the shift register that controls the serial connection to the PHY. On each shift cycle the MDIO pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register. When read, gives current shifted value. * DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. * CODE Must be written to 10 in accordance with IEEE standard 802.3. Reads as written. * REGA Register address. Specifies the register in the PHY to access. * PHYA PHY address. Normally is 0. * RW Read/Write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame. * HIGH Must be written with 1 to make a valid PHY management frame. Conforms with IEEE standard 802.3. * LOW Must be written with 0 to make a valid PHY management frame. Conforms with IEEE standard 802.3.
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EMAC Hash Address High Register
Register Name: ETH_HSH Access Type: Read/Write
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
* ADDR Hash address bits 63 to 32.
EMAC Hash Address Low Register
Register Name: ETH_HSL Access Type: Read/Write
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
* ADDR Hash address bits 31 to 0.
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EMAC Specific Address (1, 2, 3 and 4) High Register
Register Name: ETH_SA1H,...ETH_SA4H Access Type: Read/Write
31 30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
ADDR
7 6 5 4 3 2 1 0
ADDR
* ADDR Unicast addresses (1, 2, 3 and 4), Bits 47:32.
EMAC Specific Address (1, 2, 3 and 4) Low Register
Register Name: ETH_SA1L,...ETH_SA4L Access Type:
31
Read/Write
30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
7 6 5 4 3 2 1 0
ADDR
* ADDR Unicast addresses (1, 2, 3 and 4), Bits 31:0.
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EMAC Statistics Register These registers reset to zero on a read and remain at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. Block Registers
The statistics register block contains the registers found in Table 21, "Ethernet MAC Register Mapping," on page 57. Table 22. Statistics Register Block
Register Frames Transmitted OK Register Single Collision Frame Register Multiple Collision Frame Register Register Name Description ETH_FRA ETH_SCOL ETH_MCOL A 24-bit register counting the number of frames successfully transmitted. A 16-bit register counting the number of frames experiencing a single collision before being transmitted and experiencing no carrier loss nor underrun. A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun). A 24-bit register counting the number of good frames received, i.e., address recognized. A good frame is of length 64 to 1518 bytes and has no FCS, alignment or code errors. An 8-bit register counting address-recognized frames that are an integral number of bytes long, that have bad CRC and that are 64 to 1518 bytes long. An 8-bit register counting frames that: - are address-recognized, - are not an integral number of bytes long, - have bad CRC when their length is truncated to an integral number of bytes, - are between 64 and 1518 bytes long. A 16-bit register counting the number of frames experiencing deferral due to carrier sense active on their first attempt at transmission (no underrun or collision). An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. No carrier loss or underrun. A late collision is counted twice, i.e., both as a collision and a late collision. An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or underrun). An 8-bit register counting the number of frames for which carrier sense was not detected and that were maintained in half-duplex mode one slot time (512 bits) after the start of transmission (no excessive collision). An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other register is incremented. An 8-bit register counting the number of frames that are address-recognized, had RXER asserted during reception. If this counter is incremented, then no other counters are incremented. An 8-bit register counting the number of frames received exceeding 1518 bytes in length but that do not have either a CRC error, an alignment error or a code error. An 8-bit register counting the number of frames received exceeding 1518 bytes in length and having either a CRC error, an alignment error or a code error. An 8-bit register counting the number of frames received that are less than 64 bytes in length but that do not have either a CRC error, an alignment error or a code error. An 8-bit register counting the number of frames where pin ECOL was not asserted within a slot time of pin ETXEN being deasserted. This 16-bit counter is incremented every time an address-recognized frame is received but cannot be copied to memory because the receive buffer is available.
Frames Received OK Register
ETH_OK
Frame Check Sequence Error Register Alignment Error Register
ETH_SEQE ETH_ALE
Deferred Transmission Frame Register Late Collision Register
ETH_DTE ETH_LCOL
Excessive Collision Register
ETH_ECOL
Carrier Sense Error Register
ETH_CSE
Transmit Underrun Error Register
ETH_TUE
Code Error Register
ETH_CDE
Excessive Length Error Register Receive Jabber Register Undersize Frame Register
ETH_ELR ETH_RJB ETH_USF
SQE Test Error Register Discarded RX Frame Register
ETH_SQEE ETH_DRFC
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Advanced Interrupt Controller (AIC)
The AT91C140 integrates the Atmel advanced interrupt controller (AIC). The interrupt controller is connected to the fast interrupt request (nFIQ) and the standard interrupt request (NIRQ) inputs of the ARM7TDMI processor. The processor's nFIQ line can only be asserted by the external fast interrupt request input (FIQ). The nIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the two external interrupt request lines, IRQ0 to IRQ1. An 8-level priority encoder allows the user to define the priority between the different interrupt sources. Internal sources are programmed to be level-sensitive or edge-triggered. External sources can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive. Figure 21. Advanced Interrupt Controller Block Diagram
FIQ Source
Memorization
NFIQ Manager
NFIQ
Advanced Peripheral Bus (APB)
Control Logic
ARM7TDMI Core
Internal Interrupt Sources External Interrupt Sources Memorization
Prioritization Controller
NIRQ Manager
NIRQ
Table 23. Interrupt Sources
Interrupt Source 0 1 2 3 4 5 6 7 8 9 10 Interrupt Name FIQ -SWI UARTA TC0 TC1 TC2 PIOA MACA SPI IRQ0 Software Interrupt UART A Interrupt Timer Channel 0 Interrupt Timer Channel 1 Interrupt Timer Channel 2 Interrupt PIO A Interrupt MAC A Interrupt Serial Peripheral Interface External Interrupt Interrupt Description Fast Interrupt (LOWP)
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Table 23. Interrupt Sources (Continued)
Interrupt Source 11 12 13 14 15 16 - 31 Interrupt Name IRQ1 Reserved MACB UARTB PIOB Reserved MAC B Interrupt UART B Interrupt PIO B Interrupt Interrupt Description External Interrupt
Priority Controller
The nIRQ line is controlled by an 8-level priority encoder. Each source has a programmable priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest. When the AIC receives more than one unmasked interrupt at a time, the interrupt with the highest priority is serviced first. If both interrupts have equal priority, the interrupt with the lowest interrupt source number is serviced first. The current priority level is defined as the priority level of the current interrupt at the time the register AIC_IVR is read (the interrupt which will be serviced). In the case when a higher priority unmasked interrupt occurs while an interrupt already exists, there are two possible outcomes depending on whether the AIC_IVR has been read. 1. If the nIRQ line has been asserted but the AIC_IVR has not been read, then the processor will read the new higher priority interrupt handler number in the AIC_IVR register and the current interrupt level is updated. 2. If the processor has already read the AIC_IVR, then the nIRQ line is reasserted. When the processor has authorized nested interrupts to occur and reads the AIC_IVR again, it reads the new, higher priority interrupt handler address. At the same time the current priority value is pushed onto a first-in last-out stack and the current priority is updated to the higher priority. When the End of Interrupt Command Register (AIC_EOICR) is written, the current interrupt level is updated with the current interrupt level from the stack (if any). Hence, at the end of a higher priority interrupt, the AIC returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted.
Interrupt Handling
The interrupt handler must read the AIC_IVR as soon as possible. This deasserts the nIRQ request to the processor and clears the interrupt in case it is programmed to be edge-triggered. This permits the AIC to assert the nIRQ line again when a higher priority unmasked interrupt occurs. At the end of the interrupt service routine, the End of Interrupt Command Register (AIC_EOICR) must be written. This allows pending interrupts to be serviced.
Interrupt Masking
Each interrupt source, including FIQ, can be enabled or disabled using the command registers AIC_IECR and AIC_IDCR. The interrupt mask can be read in the read only register AIC_IMR. A disabled interrupt does not affect the servicing of other interrupts. All interrupt sources which are programmed to be edge-triggered (including FIQ) can be individually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR. This function of the interrupt controller is available for auto-test or software debug purposes.
Interrupt Clearing and Setting
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Standard Interrupt Sequence
It is assumed that: * The advanced interrupt controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled.
When nIRQ is asserted and if the I bit of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the IRQ link register (R14_IRQ) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_IRQ, decrementing it by 4. 2. The ARM core enters IRQ mode if it is not already. 3. When the instruction at 0x18 is executed, the Program Counter is loaded with the value read in the AIC_IVR. Reading the AIC_IVR has the following effects: Sets the current interrupt to be the pending one with the highest priority. The current level is the priority level of the current interrupt. De-asserts the nIRQ line on the processor (even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ). Automatically clears the interrupt if it has been programmed to be edge-triggered. Pushes the current level on to the stack. Returns the AIC_SVR corresponding to the current interrupt. 4. The previous step establishes a connection to the corresponding ISR. This begins by saving the link register (R14_IRQ) and the SPSR (SPSR_IRQ). Note that the link register must be decremented by 4 when it is saved if it is to be restored directly into the Program Counter at the end of the interrupt. 5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allowing re-assertion of the nIRQ to be taken into account by the core. This can occur if an interrupt with a higher priority than the current one occurs. 6. The interrupt handler then proceeds as required, saving the registers which are used and restoring them at the end. During this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. Note that if the interrupt is programmed to be level-sensitive, the source of the interrupt must be cleared during this phase. 7. The I bit in the CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The service routine should then connect to the common exit routine. 9. The End Of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists. If another interrupt with lower or equal priority than the old current level is pending, the nIRQ line is re-asserted but the interrupt sequence does not immediately start because the I bit is set in the core. 10. The SPSR (SPSR_IRQ) is restored. Finally, the saved value of the Link Register is restored directly into the PC. This has the effect of returning from the interrupt to the step previously executed, of loading the CPSR with the stored SPSR and of masking or unmasking the interrupts depending on the state saved in the SPSR (the previous state of the ARM core).
Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the mask instruction is completed (IRQ is masked).
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Fast Interrupt
The external FIQ line is the only source which can raise a fast interrupt request to the processor. Therefore it has no priority controller. It can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive in the AIC_SMR0 register. The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written into this register is available by reading the AIC_FVR register when an FIQ interrupt is raised. By storing the following instruction at address 0x0000001C, the processor will load the program counter with the interrupt handler address stored in the AIC_FVR register. LDR PC, [PC, #-&F20] Alternatively, the interrupt handler can be stored starting from address 0x0000001C as described in the ARM7TDMI datasheet. Fast Interrupt Sequence It is assumed that: * * The advanced interrupt controller has been programmed, AIC_SVR[0] is loaded with the fast interrupt service routine address and the fast interrupt is enabled. Nested fast interrupts are not needed by the user.
When nFIQ is asserted, if the F bit of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded in the FIQ link register (R14_FIQ) and the Program Counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_FIQ, decrementing it by 4. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the Program Counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has the effect of clearing the fast interrupt (source 0 connected to the FIQ line) if it has been programmed to be edge-triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step establishes a connection to the corresponding interrupt service routine. It is not necessary to save the Link Register (R14_FIQ) and the SPSR (SPSR_FIQ) if nested fast interrupts are not needed. 5. The interrupt handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level- sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the nFIQ line. 6. Finally, the Link Register (R14_FIQ) is restored into the PC after decrementing it by 4 (e.g., with instruction SUB PC, LR, #4). This has the effect of returning from the interrupt to the step previously executed, of loading the CPSR with the SPSR and of masking or unmasking the fast interrupt depending on the state saved in the SPSR.
Note: The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the interrupted instruction is completed (FIQ is masked).
Software Interrupt
Any interrupt source of the AIC can be a software interrupt. It must be programmed to be edge-triggered in order to set or clear it by writing to the AIC_ISCR and AIC_ICCR. This is totally independent of the SWI instruction of the ARM7TDMI processor.
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Spurious Interrupt
A spurious interrupt is a signal of very short duration on one of the interrupt input lines. A spurious interrupt also arises when an interrupt is triggered and masked in the same cycle. A spurious interrupt is handled by the following sequence of actions. 1. When an interrupt is active, the AIC asserts the nIRQ (or nFIQ) line and the ARM7TDMI enters IRQ (or FIQ) mode. At this moment, if the interrupt source disappears, the nIRQ (or nFIQ) line is de-asserted but the ARM7TDMI continues with the interrupt handler. 2. If the IRQ Vector Register (AIC_IVR) is read when the nIRQ is not asserted, the AIC_IVR is read with the contents of the Spurious Interrupt Vector Register. 3. If the FIQ Vector Register (AIC_FVR) is read when the nFIQ is not asserted, the AIC_FVR is read with the contents of the Spurious Interrupt Vector Register. 4. The Spurious ISR must write an End of Interrupt command as a minimum, however, it is sufficient to write to the End of Interrupt Command Register (AIC_EOICR). Until the AIC_EOICR write is received by the interrupt controller, the nIRQ (or nFIQ) line is not re-asserted. 5. This causes the ARM7TDMI to jump into the Spurious Interrupt Routine. 6. During a spurious ISR, the AIC_ISR reads 0.
Spurious Interrupt Sequence
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AIC User Interface
Base Address: 0xFF030000 with double mapping at address 0xFFFF F000 Table 1. AIC Register Mapping
Offset 0x000 0x004 - 0x07C 0x080 0x084 - 0xFC0 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 Note: Register Source Mode Register 0 Source Mode Register 1 - Source Mode Register 31 Source Vector Register 0 Source Vector Register 1 - Source Vector Register 31 IRQ Vector Register FIQ Vector Register Interrupt Status Register Interrupt Pending Register Interrupt Mask Register Core Interrupt Status Register Reserved Reserved Interrupt Enable Command Register Interrupt Disable Command Register Interrupt Clear Command Register Interrupt Set Command Register End-of-interrupt Command Register Spurious Interrupt Vector Register Register Name AIC_SMR0 AIC_SMR1 - AIC_SMR31 AIC_SVR0 AIC_SVR1 - AIC_SVR31 AIC_IVR AIC_FVR AIC_ISR AIC_IPR AIC_IMR AIC_CISR - - AIC_IECR AIC_IDCR AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU Access Read/Write Read/Write - Read/Write Read/Write Read/Write - Read/Write Read-only Read-only Read-only Read-only Read-only Read-only - - Write-only Write-only Write-only Write-only Write-only Read/Write Reset State 0 0 - 0 0 0 - 0 0 0 0
(1)
0 0 - - - - - - - 0
1. The reset value of this register depends on the level of the external IRQ lines. All other sources are cleared at reset.
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AIC Source Mode Register
Register Name: Access Type:
31 - 23 - 15 - 7 -
AIC_SMR0...AIC_SMR31 Read/Write
30 - 22 - 14 - 6 SRCTYPE 29 - 21 - 13 - 5 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 PRIOR 24 - 16 - 8 - 0
* PRIOR: Priority Level Programs the priority level for all sources except source 0 (FIQ). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the SMR0. * SRCTYPE: Interrupt Source Type Programs the input to be positive- or negative-edge triggered or positive- or negative-level sensitive. The active level or edge is not programmable for the internal sources.
SRCTYPE 0 0 1 1 0 1 0 1 Internal Sources Level-sensitive Edge-triggered Level-sensitive Edge-triggered External Sources Low-level sensitive Negative-edge triggered High-level sensitive Positive-edge triggered
AIC Source Vector Registers Register Name: Access Type:
31
AIC_SVR0...AIC_SVR31 Read/Write
30 29 28 Vector 27 26 25 24
23
22
21
20 Vector
19
18
17
16
15
14
13
12 Vector
11
10
9
8
7
6
5
4 Vector
3
2
1
0
* Vector In these registers, the user may store the addresses of the corresponding handler for each interrupt source.
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AIC Interrupt Vector Registers
Register Name: Access Type: Reset Value:
31
AIC_IVR Read-only 0
30 29 28 IRQV 27 26 25 24
23
22
21
20 IRQV
19
18
17
16
15
14
13
12 IRQV
11
10
9
8
7
6
5
4 IRQV
3
2
1
0
* IRQV The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The SVR Register (1 to 31) is indexed by the current interrupt number when the IVR register is read. When there is no interrupt, the IRQ register reads 0.
AIC FIQ Vector Register
Register Name: Access Type: Reset Value:
31
AIC_FVR Read-only 0
30 29 28 FIQV 27 26 25 24
23
22
21
20 FIQV
19
18
17
16
15
14
13
12 FIQV
11
10
9
8
7
6
5
4 FIQV
3
2
1
0
* FIQ The vector register contains the vector programmed by the user in SVR Register 0 which corresponds to FIQ.
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AIC Interrupt Status Register
Register Name: Access Type:
31 - 23 - 15 - 7 -
AIC_ISR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 27 - 19 - 11 - 3 26 - 18 - 10 - 2 IRQID 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* IRQID The interrupt status register returns the current interrupt source register. AIC Interrupt Pending Register Register Name: AIC_IPR Access Type: Read-only
31 0 23 0 15 PIOB 7 PIOA 30 0 22 0 14 UARTB 6 TC2 29 0 21 0 13 MACB 5 TC1 28 0 20 0 12 0 4 TC0 27 0 19 0 11 IRQ1 3 UARTA 26 0 18 0 10 IRQ0 2 SWI 25 0 17 0 9 SPI 1 0 24 0 16 0 8 MACA 0 FIQ
* Interrupt Pending 0 = Corresponding interrupt is not pending. 1 = Corresponding interrupt is pending.
AIC Interrupt Mask Register
Register Name: Access Type:
31 0 23 0 15 PIOB 7 PIOA
AIC_IMR Read-only
30 0 22 0 14 UARTB 6 TC2 29 0 21 0 13 MACB 5 TC1 28 0 20 0 12 0 4 TC0 27 0 19 0 11 IRQ1(1) 3 UARTA 26 0 18 0 10 IRQ0 2 SWI 25 0 17 0 9 SPI 1 0 24 0 16 0 8 MACA 0 FIQ
* Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled.
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AIC Core Interrupt Status Register
Register Name: Access Type:
31 - 23 - 15 - 7 -
AIC_CISR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 NIRQ 24 - 16 - 8 - 0 nFIQ
* nFIQ: nFIQ Status 0 = nFIQ line inactive. 1 = nFIQ line active. * NIRQ: nIRQ Status 0 = nIRQ line inactive. 1 = nIRQ line active.
AIC Interrupt Enable Command Register
Register Name: Access Type:
31 0 23 0 15 PIOB 7 PIOA
AIC_IECR Write-only
30 0 22 0 14 UARTB 6 TC2 29 0 21 0 13 MACB 5 TC1 28 0 20 0 12 0 4 TC0 27 0 19 0 11 IRQ1 3 UARTA 26 0 18 0 10 IRQ0 2 SWI 25 0 17 0 9 SPI 1 0 24 0 16 0 8 MACA 0 FIQ
* Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
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AIC Interrupt Disable Command Register
Register Name: Access Type:
31 0 23 0 15 PIOB 7 PIOA
AIC_IDCR Write-only
30 0 22 0 14 UARTB 6 TC2 29 0 21 0 13 MACB 5 TC1 28 0 20 0 12 0 4 TC0 27 0 19 0 11 IRQ1 3 UARTA 26 0 18 0 10 IRQ0 2 SWI 25 0 17 0 9 SPI 1 0 24 0 16 0 8 MACA 0 FIQ
* Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
AIC Interrupt Clear Command Register
Register Name: Access Type:
31 0 23 0 15 PIOB 7 PIOA
AIC_ICCR Write-only
30 0 22 0 14 UARTB 6 TC2 29 0 21 0 13 MACB 5 TC1 28 0 20 0 12 0 4 TC0 27 0 19 0 11 IRQ1 3 UARTA 26 0 18 0 10 IRQ0 2 SWI 25 0 17 0 9 SPI 1 0 24 0 16 0 8 MACA 0 FIQ
* Interrupt Clear 0 = No effect. 1 = Clears the corresponding interrupt.
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AIC Interrupt Set Command Register
Register Name: Access Type:
31 0 23 0 15 PIOB 7 PIOA
AIC_ISCR Write-only
30 0 22 0 14 UARTB 6 TC2 29 0 21 0 13 MACB 5 TC1 28 0 20 0 12 0 4 TC0 27 0 19 0 11 IRQ1 3 UARTA 26 0 18 0 10 IRQ0 2 SWI 25 0 17 0 9 SPI 1 0 24 0 16 0 8 MACA 0 FIQ
* Interrupt Set 0 = No effect. 1 = Sets the corresponding interrupt. AIC
End of Interrupt Command Register
AIC_EOICR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 -
Register Name: Access Type:
31 - 23 - 15 - 7 -
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written as it is only necessary to make a write to this register location to signal the end of interrupt treatment.
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AIC Spurious Interrupt Vector Register
Register Name: Access Type:
31
AIC_SPU Read/Write
30 29 28 SIQV 27 26 25 24
23
22
21
20 SIQV
19
18
17
16
15
14
13
12 SIQV
11
10
9
8
7
6
5
4 SIQV
3
2
1
0
* SIQV This register contains the 32-bit address of an interrupt routine which is used to treat cases of spurious interrupts. The programmed address is read in the AIC_IVR if it is read when the nIRQ line is not asserted. The programmed address is read in the AIC_FVR if it is read when the nFIQ line is not asserted.
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Parallel I/O Controller (PIO)
The AT91C140 integrates two PIO controllers, PIOA and PIOB. PIOA controls 32 I/O lines and PIOB controls 16 FI/O lines. Each I/O line can be programmed as an input or an output and can generate an interrupt on level change. These pins are used for several functions: * * * External I/O for Internal Peripherals Keypad Controller Function General Purpose I/O
Output Selection
The user can enable each individual I/O signal as an output with the PIO_OER and PIO_ODR registers. The output status of the I/O signals can be read in the PIO_OSR register. The direction defined has an effect only if the pin is configured to be controlled by the PIO controller. Each pin can be configured to be driven high or low. The level is defined in four different ways, according to the following conditions: * If a pin is controlled by the PIO controller and is defined as an output, the level is programmed using the PIO_SODR and PIO_CODR registers. In this case, the programmed value can be read in the PIO_ODSR register. If a pin is controlled by the PIO controller and is not defined as an output, the level is determined by the external circuit. If a pin is not controlled by the PIO controller, the state of the pin is defined by the peripheral.
I/O Levels
* *
In all cases, the level on the pin can be read in the register PIO_PDSR.
Interrupts
Each parallel I/O can be programmed to generate an interrupt when a level change occurs. This is controlled by the PIO_IER and PIO_IDR registers which enable/disable the I/O interrupt by setting/clearing the corresponding bit in PIO_IMR. When a change in level occurs, the corresponding bit in PIO_ISR is set depending on whether the pin is used as a PIO or a peripheral, and whether it is defined as input or output. If the corresponding interrupt in PIO_IMR is enabled, the PIO interrupt is asserted. When PIO_ISR is read, the register is automatically cleared.
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I/O Line Control
Figure 22. I/O Line Block Diagram
PIO_OSR
Pad Output Enable
1 0 Peripheral Output Enable
PIO_PSR PIO_ODSR Pad Output 1 0
Pad
Peripheral Output
Pad Input 0 Peripheral Input 1
PIO_PSR
PIO_PDSR
Event Detection PIO_ISR
PIO_IMR
PIOIRQ
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Parallel I/O Controller (PIO) User Interface
Each individual I/O is associated with a bit position in the parallel I/O user interface registers. Each of these registers is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read as zero. Table 24. PIO Controller Memory Map
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C Notes: Register Name PIO_PER PIO_PDR PIO_PSR - PIO_OER PIO_ODR PIO_OSR - - - - - PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR PIO_ISR
(2) (1)
Description PIO Enable Register PIO Disable Register PIO Status Register Reserved Output Enable Register Output Disable Register Output Status Register Reserved Reserved Reserved Reserved Reserved Set Output Data Register Clear Output Data Register Output Data Status Register Pin Data Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register
Access Write-only Write-only Read-only - Write-only Write-only Read-only - - - - - Write-only Write-only Read-only Read-only Write-only Write-only Read-only Read-only
Reset Value - - - - - - 0x0 - - - 0x0 - - - 0x0 See Note 1 - - - See Note 2
1. The reset value of this register depends on the level of the external pins at reset. 2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have occurred on any pins between the reset and the read.
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PIO Enable Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_PER Write-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register is used to enable individual pins to be controlled by the PIO controller instead of the associated peripheral. When the PIO is enabled, the associated peripheral (if any) is held at logic zero. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 0 = No effect.
PIO Disable Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_PDR Write-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral function is enabled on the corresponding pin. 1 = Disables PIO control (enables peripheral control) on the corresponding pin. 0 = No effect.
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PIO Status Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_PSR Read-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or disabled. 1 = PIO is active on the corresponding line (peripheral is inactive). 0 = PIO is inactive on the corresponding line (peripheral is active).
PIO Output Enable Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_OER Write-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register is used to enable PIO output drivers. If the pin is driven by a peripheral, there is no effect on the pin but the information is stored. The register is programmed as follows: 1 = Enables the PIO output on the corresponding pin. 0 = No effect.
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PIO Output Disable Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_ODR Write-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register is used to disable PIO output drivers. If the pin is driven by the peripheral, there is no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Disables the PIO output on the corresponding pin. 0 = No effect.
PIO Output Status Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_OSR Read-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows: 1 = The corresponding PIO is output on this line. 0 = The corresponding PIO is input on this line.
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PIO Set Output Data Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_SODR Write-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is set. 0 = No effect.
PIO Clear Output Data Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_CODR Write-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is cleared. 0 = No effect.
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PIO Output Data Status Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_ODSR Read-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effective only if the pin is controlled by the PIO Controller and only if the pin is defined as an output. 1 = The output data for the corresponding line is programmed to 1. 0 = The output data for the corresponding line is programmed to 0.
PIO Pin Data Status Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_PDSR Read-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register shows the state of the physical pin of the chip. The pin values are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The register reads as follows: 1 = The corresponding pin is at logic 1. 0 = The corresponding pin is at logic 0.
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PIO Interrupt Enable Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_IER Write-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register is used to enable PIO interrupts on the corresponding pin. It has an effect whether PIO is enabled or not. 1 = Enables an interrupt when a change of logic level is detected on the corresponding pin. 0 = No effect.
PIO Interrupt Disable Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_IDR Write-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register is used to disable PIO interrupts on the corresponding pin. It has an effect whether the PIO is enabled or not. 1 = Disables the interrupt on the corresponding pin. Logic level changes are still detected. 0 = No effect.
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PIO Interrupt Mask Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_IMR Read-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR. 1 = Interrupt is enabled on the corresponding pin. 0 = Interrupt is not enabled on the corresponding pin.
PIO Interrupt Status Register
Register Name: Access Type:
31 P31 23 P23 15 P15 7 P7 30 P30 22 P22 14 P14 6 P6
PIO_ISR Read-only
29 P29 21 P21 13 P13 5 P5 28 P28 20 P20 12 P12 4 P4 27 P27 19 P19 11 P11 3 P3 26 P26 18 P18 10 P10 2 P2 25 P25 17 P17 9 P9 1 P1 24 P24 16 P16 8 P8 0 P0
This register indicates for each pin when a logic value change has been detected (rising or falling edge). This is valid whether the PIO is selected for the pin or not and whether the pin is an input or an output. The register is reset to zero following a read and at reset. 1 = At least one input change has been detected on the corresponding pin since the register was last read. 0 = No input change has been detected on the corresponding pin since the register was last read.
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Universal Asynchronous Receiver Transmitter (UART)
The AT91C140 provides two identical full-duplex Universal Asynchronous Receiver Transmitters, UART A and UART B. These peripherals sit on the APB bus but are also connected to the ASB bus (and hence external memory) via a dedicated PDC. The main features are: * * * * * * * * Programmable Baud Rate Generator Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes Interrupt Generation Two Dedicated Peripheral Data Controller Channels 6-, 7- and 8-bit Character Length Modem Control Signals
Block Diagram
Figure 23. UART Block Diagram
ARM ASB Peripheral Data Controller Peripheral Bridge Receive Channel Transmit Channel
UART APB Control Logic Receiver RXD
PIO
UART Interrupt
Interrupt Control
ACLK Baud Rate Generator ACLK/8 Baud Rate Clock
Transmitter
TXD
SCK NRTS Modem Control NCTS NRI NDTR NDSR NDCD
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Pin Description
Each UART channel has external signals as defined in Table 25. Table 25. UART Pins
Signal Name SCK TXD RXD NRTS NCTS NDTR NDSR NDCD NRI Description UART Serial Clock. Can be configured as input or output. See US_MR Transmit Serial Data Receive Serial Data Request to Send Clear to Send Data Terminal Ready Data Set Ready Data Carrier Detect Ring Indicator Type I/O Output Input Output Input Output Input Input Input
Baud Rate Generator
The baud rate generator provides the bit period clock (the baud rate clock) to both the receiver and the transmitter. The baud rate generator can select between external and internal clock sources. The external clock source is SCK. The internal clock sources can be either the ARM Clock (ACLK) or the ARM Clock divided by 8 (ACLK/8).
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (ACLK) period. The external clock frequency must be at least 2.5 times lower than the system clock.
The selected clock is divided by 16 times the value (CD) written in US_BRGR (Baud Rate Generator Register). If US_BRGR is set to 0, the baud rate clock is disabled.
Baud Rate = Selected Clock 16 x CD
Table 26. Clock Generator Table with Crystal Frequency of 16 MHz
Required Baud Rate (bps) 9600 19200 38400 57600 115200 CD 260.42 130.21 65.10 43.41 21.70 Actual CD 260 130 65 43 22 Actual Baud Rate (bps) 9615.385 19230.77 38461.54 58139.53 113636.40 Error (bps) 15,38 30.77 61.54 539.53 -1163.64 % Error 0.16 0.16 0.16 0.94 -1.36
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Figure 24. Baud Rate Generator
USCLKS [0] CD CD ACLK ACLK/8 0 1
CLK
16-bit Counter
OUT
>1 1 0 0 Divide by 16 Baud Rate Clock
Receiver Operations
The UART detects the start of a received character by sampling the RXD signal until it detects a valid start bit. A low level (space) on RXD is interpreted as a valid start bit if it is detected for more than seven cycles of the sampling clock, which is 16 times the baud rate. Hence, a space which is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the RXD at the theoretical mid-point of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the sampling point is eight cycles (0.5-bit periods) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 25. Start Bit Detection
16 x Baud Rate Clock RXD
Sampling
True Start Detection
D0
Figure 26. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5-bit periods 1-bit period
RXD
Sampling
D0 D1 True Start Detection
D2
D3
D4
D5
D6
D7 Parity Bit
Stop Bit
Receiver Ready
When a complete character is received, it is transferred to the US_RHR and the RXRDY status bit in US_CSR is set. If US_RHR has not been read since the last transfer, the OVRE status bit in US_CSR is set.
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Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits in accordance with the field PAR in US_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in US_CSR is set. If a character is received with a stop bit at low level and with at least one data bit at high level, a framing error is generated. This sets FRAME in US_CSR. This function allows an idle condition on the RXD line to be detected. The maximum delay for which the UART should wait for a new character to arrive while the RXD line is inactive (high level) is programmed in US_RTOR. When this register is set to 0, no timeout is detected. Otherwise, the receiver waits for a first character and then initializes a counter which is decremented at each bit period and reloaded at each byte reception. When the counter reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first character with the STTTO (Start Time-out) bit in US_CR. Calculation of time-out duration: Duration = Value x 4 x Bit Period
Framing Error
Time-out
Transmitter
Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of the serial clock. The number of data bits is selected in the CHRL field in US_MR. The parity bit is set according to the PAR field in US_MR. The number of stop bits is selected in the NBSTOP field in US_MR. When a character is written to US_THR, it is transferred to the Shift Register as soon as it is empty. When the transfer occurs, the TXRDY bit in US_CSR is set until a new character is written to US_THR. If the Transmit Shift Register and US_THR are both empty, the TXEMPTY bit in US_CSR is set. Figure 27. Character Transmission
Example: 8-bit, parity enabled 1 stop Baud Rate Clock TXD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
Time-guard
The time-guard function allows the transmitter to insert an idle state on the TXD line between two characters. The duration of the idle state is programmed in US_TTGR. When this register is set to zero, no time-guard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in US_TTGR.
Idle state duration between two characters = Time-guard value x Bit period
Channel Modes
The UART can be programmed to operate in three different test modes using the field CHMODE in US_MR.
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Automatic echo mode allows bit-by-bit re-transmission. When a bit is received on the RXD line, it is sent to the TXD line. Programming the transmitter has no effect. Local loopback mode allows the transmitted characters to be received. TXD and RXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The RXD pin level has no effect and the TXD pin is held high, as in idle state. Remote loopback mode directly connects the RXD pin to the TXD pin. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 28. Channel Modes
Automatic Echo Receiver RXD
Transmitter
Disabled
TXD
Local Loopback Receiver
Disabled
RXD
VDD Transmitter
Disabled
TXD
Remote Loopback Receiver
VDD Disabled RXD
Transmitter
Disabled
TXD
Peripheral Data Controller
Each UART channel is closely connected to a corresponding peripheral data controller channel. One is dedicated to the receiver, the other is dedicated to the transmitter. The PDC channel is programmed using US_TPR and US_TCR for the transmitter and US_RPR and US_RCR for the receiver. The status of the PDC is given in US_CSR by the ENDTX bit for the transmitter and by the ENDRX bit for the receiver. The pointer registers US_TPR and US_RPR are used to store the address of the transmit or receive buffers. The counter registers US_TCR and US_RCR are used to store the size of these buffers. The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is triggered by TXRDY. When a transfer is performed, the counter is decremented and the pointer is incremented. When the counter reaches 0, the status bit is set 99
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(ENDRX for the receiver, ENDTX for the transmitter in US_CSR) and can be programmed to generate an interrupt. Transfers are then disabled until a new non-zero counter value is programmed.
Modem Control and Status Signals
NCTS: Clear to Send When low, this indicates that the modem or data set is ready to exchange data. The NCTS signal is a modem status input; its conditions can be tested by the CPU reading bit 4 (CTS) of the Modem Status Register. Bit 4 is the complement of the NCTS signal. Bit 0 (DCTS) of the Modem Status Register indicates whether the NCTS input has changed state since the previous read of the Modem Status Register. NCTS has no effect on the transmitter. When low, this indicates that the data carrier has been detected by the modem or data set. The NDCD signal is a modem status input; its condition can be tested by the CPU reading bit 7 (DCD) of the Modem Status Register. Bit 7 is the complement of the NDCD signal. Bit 3 (DDCD) of the Modem Status Register indicates whether the NDCD input pin has changed since the previous reading of the Modem Status Register. NDCD has no effect on the receiver. When low, this informs the modem or data set that the UART is ready to communicate. The NDSR signal is a modem status input; its condition can be tested by the CPU reading bit 5 (DSR) of the Modem Status Register. Bit 5 is the complement of the NDSR signal. Bit 1 (DDSR of the Modem Status Register) indicates whether the NDSR input has changed state since the previous read of the Modem Status Register. When low, this informs the modem or data set that the UART is ready to communicate. The NDTR output signal can be set to active low by programming bit 0 (DTR) of the Modem Control Register to a high level. A master reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. When low, this indicates that a telephone ringing signal has been received by the modem or data set. The NRI signal is a modem status input; its condition can be tested by the CPU reading bit 6 (RI) of the Modem Status Register. Bit 6 is the complement of the NRI signal. Bit 2 (TERI) of the Modem Status Register indicates whether the NRI input signal has changed from a low to a high state since the previous read of the Modem Status Register. When low, this informs the modem or data set that the UART is ready to exchange data. The NRTS output signal can be set to an active low by programming bit 1 (RTS) of the Modem Control Register. A master reset operation sets this signal to its inactive (high) state.
NDCD: Data Carrier Detect
NDSR: Data Set Ready
NDTR: Data Terminal Ready
NRI: Ring Indicator
NRTS: Request to Send
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Universal Asynchronous Receiver/Transmitter (UART) User Interface
Table 27. UART Memory Map
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 Register Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR - US_RPR US_RCR US_TPR US_TCR US_MC US_MS Description Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Time-guard Register Reserved Receive Pointer Register Receive Counter Register Transmit Pointer Register Transmit Counter Register Modem Control Register Modem Status Register Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write Read/Write Read/Write - Read/Write Read/Write Read/Write Read/Write Write-only Read-only Reset Value - 0 - - 0 0x18 0 - 0 0 0 - 0 0 0 0 -
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UART Control Register
Name: Access Type:
31 - 23 - 15 - 7 TXDIS 30 - 22 - 14 - 6 TXEN
US_CR Write-only
29 - 21 - 13 - 5 RXDIS 28 - 20 - 12 - 4 RXEN 27 - 19 - 11 - 3 RSTTX 26 - 18 - 10 - 2 RSTRX 25 - 17 - 9 - 1 - 24 - 16 - 8 RSTSTA 0 -
* RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset. * RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset. * RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. * RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. * TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. * TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. * RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.
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UART Mode Register
Name: Access Type:
31 - 23 - 15 CHMODE 7 CHRL 6 5 USCLKS 30 - 22 - 14
US_MR Read/Write
29 - 21 - 13 NBSTOP 4 3 - 28 - 20 - 12 27 - 19 - 11 26 - 18 - 10 PAR 2 - 1 - 25 - 17 - 9 24 - 16 - 8 - 0 -
* USCLKS: Clock Selection
USCLKS 0 0 1 0 1 X Selected Clock ACLK ACLK/8 External (SCK)
* CHRL: Character Length
CHRL 0 0 1 1 0 1 0 1 Character Length Five bits Six bits Seven bits Eight bits
* PAR: Parity Type
PAR 0 0 0 0 1 0 0 1 1 0 0 1 0 1 x Parity Type Even parity Odd parity Parity forced to 0 (space) Parity forced to 1 (mark) No parity
* NBSTOP: Number of Stop Bits
NBSTOP 0 0 1 1 0 1 0 1 1 stop bit 1.5 stop bits 2 stop bits Reserved
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* CHMODE: Channel Mode
CHMODE 0 0 1 0 1 0 Mode Description Normal Mode The UART channel operates as an Rx/Tx UART. Automatic Echo Receiver data input is connected to TXD pin. Local Loopback Transmitter output signal is connected to receiver input signal. Remote Loopback RXD pin is internally connected to TXD pin.
1
1
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UART Interrupt Enable Register
Name: Access Type:
31 - 23 - 15 - 7 PARE 30 - 22 - 14 - 6 FRAME
US_IER Write-only
29 - 21 - 13 - 5 OVRE 28 - 20 - 12 - 4 ENDTX 27 - 19 - 11 - 3 ENDRX 26 - 18 - 10 DMSI 2 - 25 - 17 - 9 TXEMPTY 1 TXRDY 24 - 16 - 8 - 0 RXRDY
* RXRDY: Enable RXRDY Interrupt * TXRDY: Enable TXRDY Interrupt * ENDRX: Enable End of Receive Transfer Interrupt * ENDTX: Enable End of Transmit Transfer Interrupt * OVRE: Enable Overrun Error Interrupt * FRAME: Enable Framing Error Interrupt * PARE: Enable Parity Error Interrupt * TXEMPTY: Enable TXEMPTY Interrupt * DMSI: Delta Modem Interrupt 0 = No effect. 1 = Enables the corresponding interrupt.
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UART Interrupt Disable Register
Name: Access Type:
31 - 23 - 15 - 7 PARE 30 - 22 - 14 - 6 FRAME
US_IDR Write-only
29 - 21 - 13 - 5 OVRE 28 - 20 - 12 - 4 ENDTX 27 - 19 - 11 - 3 ENDRX 26 - 18 - 10 DMSI 2 - 25 - 17 - 9 TXEMPTY 1 TXRDY 24 - 16 - 8 - 0 RXRDY
* RXRDY: Disable RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Disable End of Receive Transfer Interrupt * ENDTX: Disable End of Transmit Transfer Interrupt * OVRE: Disable Overrun Error Interrupt * FRAME: Disable Framing Error Interrupt * PARE: Disable Parity Error Interrupt * TXEMPTY: Disable TXEMPTY Interrupt * DMSI: Disable Delta Modem Interrupt 0 = No effect. 1 = Disables the corresponding interrupt.
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UART Interrupt Mask Register
Name: Access Type:
31 - 23 - 15 - 7 PARE 30 - 22 - 14 - 6 FRAME
US_IMR Read-only
29 - 21 - 13 - 5 OVRE 28 - 20 - 12 - 4 ENDTX 27 - 19 - 11 - 3 ENDRX 26 - 18 - 10 DMSI 2 RXBRK 25 - 17 - 9 TXEMPTY 1 - 24 - 16 - 8 - 0 RXRDY
* RXRDY: RXRDY Interrupt Mask * TXRDY: TXRDY Interrupt Mask * ENDRX: End of Receive Transfer Interrupt Mask * ENDTX: End of Transmit Transfer Interrupt Mask * OVRE: Overrun Error Interrupt Mask * FRAME: Framing Error Interrupt Mask * PARE: Parity Error Interrupt Mask * TXEMPTY: TXEMPTY Interrupt Mask * DMSI: Delta Modem Status Indication Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
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UART Channel Status Register
Name: Access Type:
31 - 23 - 15 - 7 PARE 30 - 22 - 14 - 6 FRAME
US_CSR Read-only
29 - 21 - 13 - 5 OVRE 28 - 20 - 12 - 4 ENDTX 27 - 19 - 11 - 3 ENDRX 26 - 18 - 10 DMSI 2 - 25 - 17 - 9 TXEMPTY 1 TXRDY 24 - 16 - 8 - 0 RXRDY
* RXRDY: Receiver Ready 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. 1 = At least one complete character has been received and the US_RHR has not yet been read. * TXRDY: Transmitter Ready 0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register. 1 = US_THR is empty and there is no break request pending TSR availability. Equal to zero when the UART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one. * ENDRX: End-of-receive Transfer 0 = The end-of-transfer signal from the PDC channel dedicated to the receiver is inactive. 1 = The end-of-transfer signal from the PDC channel dedicated to the receiver is active. * ENDTX: End-of-transmit Transfer 0 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is inactive. 1 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is active. * OVRE: Overrun Error 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last reset status bits command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last reset status bits command. * FRAME: Framing Error 0 = No stop bit has been detected low since the last reset status bits command. 1 = At least one stop bit has been detected low since the last reset status bits command. * PARE: Parity Error 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bit" command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits command. * TXEMPTY: Transmitter Empty 0 = There are characters in either US_THR or the Transmit Shift Register or a break is being transmitted. 1 = There are no characters in US_THR and the Transmit Shift Register and break is not active. Equal to zero when the UART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one. * DMSI: Delta Modem Status Indication Interrupt 0 = No effect. 1 = There has been a change in the modem status delta bits since the last reset status bits command.
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UART Receiver Holding Register
Name: Access Type:
31 - 23 - 15 - 7 30 - 22 - 14 - 6
US_RHR Read-only
29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* RXCHR: Received Character Last character received if RXRDY is set. When number of data bits is less than eight, the bits are right-aligned.
UART Transmitter Holding Register
Name: Access Type:
31 - 23 - 15 - 7 30 - 22 - 14 - 6
US_THR Write-only
29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than eight, the bits are right-aligned.
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UART Baud Rate Generator Register
Name: Access Type:
31 - 23 - 15 30 - 22 - 14
US_BRGR Read/Write
29 - 21 - 13 28 - 20 - 12 CD 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 CD
3
2
1
0
* CD: Clock Divisor This register has no effect if synchronous mode is selected with an external clock.
CD 0 1 2 to 65535 Effect Disables clock Clock divisor bypass Baud rate = Selected clock/(16 x CD)
UART Receive Pointer Register
Name: Access Type:
31 30
US_RPR Read/Write
29 28 RXPTR 27 26 25 24
23
22
21
20 RXPTR
19
18
17
16
15
14
13
12 RXPTR
11
10
9
8
7
6
5
4 RXPTR
3
2
1
0
* RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer.
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UART Receive Counter Register
Name: Access Type: Reset Value:
31 - 23 - 15 30 - 22 - 14
US_RCR Read/Write 0x0
29 - 21 - 13 28 - 20 - 12 RXCTR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 RXCTR
3
2
1
0
* RXCTR: Receive Counter RXCTR must be loaded with the size of the receive buffer. 0 =Stop peripheral data transfer dedicated to the receiver. 1 - 65535: Start peripheral data transfer if RXRDY is active.
UART Transmit Pointer Register
Name: Access Type: Reset Value:
31 30
US_TPR Read/Write 0x0
29 28 TXPTR 27 26 25 24
23
22
21
20 TXPTR
19
18
17
16
15
14
13
12 TXPTR
11
10
9
8
7
6
5
4 TXPTR
3
2
1
0
* TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer.
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UART Transmit Counter Register
Name: Access Type: Reset Value:
31 - 23 - 15 30 - 22 - 14
US_TCR Read/Write 0x0
29 - 21 - 13 28 - 20 - 12 TXCTR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 TXCTR
3
2
1
0
* TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0 =Stop peripheral data transfer dedicated to the transmitter. 1 - 65535: Start peripheral data transfer if TXRDY is active.
Modem Control Register
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 -
US_MC Write-only Undefined
29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 RTS 24 - 16 - 8 - 0 DTR
This register controls the interface with the modem or data set (or a peripheral device emulating a modem). The contents of the Control Register are indicated below. * DTR: Data Terminal Ready This bit controls the NDTR output. When bit 0 is set to a logic 1, the NDTR output is forced to a logic 0. When bit 0 is reset to a logic 0, the NDTR output is forced to a logic 1. The NDTR output of the UART can be applied to an EIA inverting line driver to obtain proper polarity input at the succeeding modem or data set. * RTS: Request to Send This bit controls the NRTS output. Bit 1 affects the NRTS output in a manner identical to that described above for bit 0.
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Modem Status Register
Register Name: Access Type:
31 - 23 - 15 - 7 DCD 30 - 22 - 14 - 6 RI
US_MS Read-only
29 - 21 - 13 - 5 DSR 28 - 20 - 12 - 4 CTS 27 - 19 - 11 - 3 DDCD 26 - 18 - 10 - 2 TERI 25 - 17 - 9 - 1 DDSR 24 - 16 - 8 - 0 DCTS
This register provides the current state of the control lines from the modem (or peripheral device) to the CPU. In addition to this current-state information, four bits of the Modem Status Register provide change information. These bits are set to a logic 1 whenever a control input from the modem changes state. They are reset to logic 0 whenever the CPU reads the Modem Status Register. * DCTS: Delta Clear to Send Bit 0 indicates that the NCTS input to the chip has changed state since the last time it was read by the CPU. * DDSR: Delta Data Set Ready Bit 1 indicates that the NDSR input to the chip has changed state since the last time it was read by the CPU. * TERI: Trailing Edge Ring Indicator Bit 2 indicates that the NRI input to the chip has changed from a low to a high state. * DDCD: Delta Data Carrier Detect Bit 3 indicates that the NDCD input has changed state. Note that whenever bit 0, 1, 2, or 3 is set to logic 1, a modem status interrupt is generated. This is reflected in the modem status register. * CTS: Clear to Send This bit is the complement of the Clear to Send (NCTS) input. * DSR: Data Set Ready This bit is the complement of the Data Set Ready (NDSR) input. * RI: Ring Indicator This bit is the complement of the Ring Indicator (NRI) input. * DCD: Data Carrier Detect This bit is the complement of the Data Carrier Detect (NDCD) input.
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Timer/Counter (TC)
The AT91C140 features a timer/counter block that includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation. Each timer/counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals that can be configured by the user. Each channel drives an internal interrupt signal that can be programmed to generate processor interrupts via the AIC. The timer/counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each timer/counter channel, allowing them to be chained.
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Block Diagram
Figure 29. Timer/Counter Block Diagram
ACLK/2 ACLK/8 ACLK/32 ACLK/128 ACLK/1024
Parallel I/O Controller TCLK0 TIOA1 TIOA2 TCLK1 TCLK2 XC0 XC1 XC2 TC0XC0S
SYNC
TCLK0 TCLK1 TCLK2 TIOA0 TIOB0
Timer/Counter Channel 0
TIOA
TIOA0
TIOB
TIOB0 INT
TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S
SYNC
Timer/Counter Channel 1
TIOA
TIOA1
TIOB
TIOB1 INT
TIOA1 TIOB1
TCLK0 TCLK1 TCLK2 TIOA0 TIOA1
XC0 XC1 XC2 TC2XC2S
Timer/Counter Channel 2
TIOA
TIOA2
TIOB
TIOB2
SYNC
TIOA2 TIOB2
INT
Timer/Counter Block Advanced Interrupt Controller
Signal Name Description
Table 28. Timer Counter Signal Description
Channel Signal XC0, XC1, XC2 TIOA TIOB INT SYNC Description External clock inputs Capture mode: General-purpose input Waveform mode: General-purpose output Capture mode: General-purpose input Waveform mode: General-purpose input/output Interrupt signal output Synchronization input signal Type I I O I O O I
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Table 28. Timer Counter Signal Description
Block Signal TCLK0, TCLK1, TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 Note: External clock inputs TIOA signal for Channel 0 TIOB signal for Channel 0 TIOA signal for Channel 1 TIOB signal for Channel 1 TIOA signal for Channel 2 TIOB signal for Channel 2 I I/O I/O I/O I/O I/O I/O
After a hardware reset, the timer/counter block pins are controlled by the PIO controller. They must be configured to be controlled by the peripheral before being used.
Description
Counter
The three timer/counter channels are independent and identical in operation. Each timer/counter channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.
Clock Selection
At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). Each channel can independently select an internal or external clock source for its counter: * * Internal clock signals: ACLK/2, ACLK/8, ACLK/32, ACLK/128, ACLK/1024 External clock signals: XC0, XC1 or XC2
The selected clock can be inverted with the CLKI bit in TC_CMR (Channel Mode). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (ACLK) period. The external clock frequency must be at least 2.5 times lower than the system clock (ACLK).
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Figure 30. Clock Selection
CLKS CLKI ACLK/2 ACLK/8 ACLK/32 ACLK/128 ACLK/1024 XC0 XC1 XC2
Selected Clock
BURST
1
Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. 1. The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In capture mode, it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In waveform mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. 2. The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in capture mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in waveform mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have an effect only if the clock is enabled.
Timer/Counter Operating Modes
Each timer/counter channel can operate independently in two different modes: 1. Capture mode allows measurement on signals 2. Waveform mode allows wave generation The timer/counter operating mode is programmed with the WAVE bit in the TC Mode Register. In capture mode, TIOA and TIOB are configured as inputs. In waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger.
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Figure 31. Clock Control
Selected Clock Trigger
CLKSTA
CLKEN
CLKDIS
Q Q S R
S R
Counter Clock
Stop Event
Disable Event
Trigger
A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: 1. Software trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. 2. SYNC: Each channel has a synchronization signal, SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. 3. Compare RC trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The timer/counter channel can also be configured to have an external trigger. In capture mode, the external trigger signal can be selected between TIOA and TIOB. In waveform mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the system clock (ACLK) period in order to be detected. Whatever the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value may not read zero just after a trigger, especially when a low-frequency signal is selected as the clock.
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Capture Operating Mode
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture mode allows the TC Channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are inputs. Figure 32 shows the configuration of the TC Channel when programmed in capture mode. Capture Registers A and B (RA and RB) Registers A and B are used as capture registers; thus, they can be loaded with the counter value when a programmable event occurs on the TIOA signal. The parameter LDRA in TC_CMR defines the TIOA edge for the loading of Register A, and the parameter LDRB defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger. Parameter ETRGEDG defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. Status Register The following bits in the status register are significant in capture operating mode. * CPCS: RC Compare Status There has been an RC Compare match at least once since the last read of the status. * * COVFS: Counter Overflow Status The counter has attempted to count past $FFFF since the last read of the status. LOVRS: Load Overrun Status RA or RB has been loaded at least twice without any read of the corresponding register since the last read of the status. * * * LDRAS: Load RA Status RA has been loaded at least once without any read since the last read of the status. LDRBS: Load RB Status RB has been loaded at least once without any read since the last read of the status. ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status.
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Figure 32. Capture Mode
TCCLKS CLKI ACLK/2 ACLK/8 ACLK/32 ACLK/128 ACLK/1024 XC0 XC1 XC2 LDBSTOP BURST Register C Capture Register A 16-bit Counter
CLK OVF RESET
CLKSTA
CLKEN
CLKDIS
Q Q S R
S R
LDBDIS
1
Capture Register B
Compare RC =
SWTRG
SYNC ABETRG ETRGEDG MTIOB Edge Detector LDRA Edge Detector
Trig
CPCTRG
TIOB
LDRB Edge Detector If RA is loaded
ETRGS
COVFS
LOVRS
LDRAS
LDRBS
TC_SR
CPCS
MTIOA If RA is not loaded or RB is loaded TIOA
TC_IMR
Timer/Counter Channel
INT
Waveform Operating Mode
This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). Waveform operating mode allows the TC channel to generate 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or to generate different types of one-shot or repetitive pulses. In this mode, TIOA is configured as output and TIOB is defined as output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 33 on page 123 shows the configuration of the TC channel when programmed in waveform operating mode.
Compare Register A, B and C (RA, RB, and RC)
In waveform operating mode, RA, RB and RC are all used as compare registers. RA Compare is used to control the TIOA output. RB Compare is used to control the TIOB (if configured as output). RC Compare can be programmed to control TIOA and/or TIOB outputs. RC Compare can also stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR).
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As in capture mode, RC Compare can also generate a trigger if CPCTRG = 1. A trigger resets the counter so RC can control the period of PWM waveforms. External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The parameter EEVT in TC_CMR selects the external trigger. The parameter EEVTEDG defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as output and the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in capture mode, the SYNC signal, the software trigger and the RC compare trigger are also available as triggers. Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. Table 29 and Table 30 show which parameter in TC_CMR is used to define the effect of each event.
Table 29. TIOA Events
Parameter ASWTRG AEEVT ACPC ACPA TIOA Event Software trigger External event RC compare RA compare
Table 30. TIOB Events
Parameter BSWTRG BEEVT BCPC BCPB TIOB Event Software trigger External event RC compare RB compare
If two or more events occur at the same time, the priority level is defined as follows: 1. Software trigger 2. External event 3. RC compare 4. RA or RB compare
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Status
The following bits in the status register are significant in waveform mode: * * * * * CPAS: RA Compare Status There has been a RA Compare match at least once since the last read of the status CPBS: RB Compare Status There has been a RB Compare match at least once since the last read of the status CPCS: RC Compare Status There has been a RC Compare match at least once since the last read of the status COVFS: Counter Overflow Counter has attempted to count past $FFFF since the last read of the status ETRGS: External Trigger External trigger has been detected since the last read of the status
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BURST Register A Register B Register C
ASWTRG Compare RA = Compare RC = 16-bit Counter
CLK RESET OVF
1
Compare RB =
SWTRG
BCPC Trig BCPB CPCTRG MTIOB
SYNC
EEVT BEEVT EEVTEDG ENETRG ETRGS COVFS TC_SR CPAS Edge Detector TC_IMR CPCS CPBS
Output Controller
BSWTRG
TIOB
Timer/Counter Channel
AT91C140
INT
Output Controller
6069A-ATARM-05/04
CLKSTA ACPC CLKI CLKEN CLKDIS
TCCLKS
ACLK/2
ACLK/8
Figure 33. Waveform Mode
ACLK/32
Q
CPCDIS
S R
ACPA MTIOA
ACLK/128
ACLK/1024
Q R
CPCSTOP AEEVT
S
XC0
XC1
TIOA
XC2
TIOB
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Timer/Counter (TC) User Interface
Table 31. TC Global Memory Map
Offset 0x00 0x40 0x80 0xC0 0xC4 TC_BCR TC_BMR Register Name Channel/Register TC Channel 0 TC Channel 1 TC Channel 2 TC Block Control Register TC Block Mode Register Access Reset Value See Table 32 See Table 32 See Table 32 Write-only Read/Write - 0
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in Table 32. The offset of each of the channel registers in Table 32 is in relation to the offset of the corresponding channel as specified in Table 31. Table 32. TC Channel Memory Map
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C Note: TC_CVR TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR Register Name TC_CCR TC_CMR Description Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Read/Write Read/Write
(1)
Access Write-only Read/Write
Reset Value - 0 - - 0 0 0 0 - - - 0
Read/Write(1) Read/Write Read-only Write-only Write-only Read-only
1. Read only if WAVE = 0.
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TC Block Control Register
Register Name: Access Type:
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 -
TC_BCR Write-only
29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 SYNC
* SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
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TC Block Mode Register
Register Name: Access Type:
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 -
TC_BMR Read/Write
29 - 21 - 13 - 5 TC2XC2S 28 - 20 - 12 - 4 27 - 19 - 11 - 3 TC1XC1S 26 - 18 - 10 - 2 25 - 17 - 9 - 1 TC0XC0S 24 - 16 - 8 - 0
* TC0XC0S: External Clock Signal 0 Selection
TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 None TIOA1 TIOA2
* TC1XC1S: External Clock Signal 1 Selection
TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2
* TC2XC2S: External Clock Signal 2 Selection
TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1
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TC Channel Control Register
Register Name: Access Type:
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 -
TC_CCR Write-only
29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SWTRG 25 - 17 - 9 - 1 CLKDIS 24 - 16 - 8 - 0 CLKEN
* CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. * CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. * SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and clock is started.
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TC Channel Mode Register: Capture Mode
Register Name: Access Type:
31 - 23 - 15 WAVE 7 LDBDIS 30 - 22 - 14 CPCTRG 6 LDBSTOP
TC_CMR Read/Write
29 - 21 - 13 - 5 BURST 28 - 20 - 12 - 4 11 - 3 CLKI 27 - 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 - 18 25 - 17 LDRA 8 24 - 16
* TCCLKS: Clock Selection
TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected ACLK/2 ACLK/8 ACLK/32 ACLK/128 ACLK/1024 XC0 XC1 XC2
* CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection
BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock.
* LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. * LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs.
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* ETRGEDG: External Trigger Edge Selection
ETRGEDG 0 0 1 1 0 1 0 1 Edge None Rising edge Falling edge Each edge
* ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. * CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. * WAVE 0 = Capture mode is enabled. 1 = Capture mode is disabled (waveform mode is enabled). * LDRA: RA Loading Selection
LDRA 0 0 1 1 0 1 0 1 Edge None Rising edge of TIOA Falling edge of TIOA Each edge of TIOA
* LDRB: RB Loading Selection
LDRB 0 0 1 1 0 1 0 1 Edge None Rising edge of TIOA Falling edge of TIOA Each edge of TIOA
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TC Channel Mode Register: Waveform Mode
Register Name: Access Type:
31 BSWTRG 23 ASWTRG 15 WAVE 7 CPCDIS 14 CPCTRG 6 CPCSTOP 13 - 5 BURST 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS 30
TC_CMR Read/Write
29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24
* TCCLKS: Clock Selection
TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected ACLK/2 ACLK/8 ACLK/32 ACLK/128 ACLK/1024 XC0 XC1 XC2
* CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection
BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock.
* CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. * CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC.
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* EEVTEDG: External Event Edge Selection
EEVTEDG 0 0 1 1 0 1 0 1 Edge None Rising edge Falling edge Each edge
* EEVT: External Event Selection
EEVT 0 0 1 1 Note: 0 1 0 1 Signal Selected as External Event TIOB XC0 XC1 XC2 TIOB Direction Input(1) Output Output Output
If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
* ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. * CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. * WAVE 0 = Waveform mode is disabled (Capture mode is enabled). 1 = Waveform mode is enabled. * ACPA: RA Compare Effect on TIOA
ACPA 0 0 1 1 0 1 0 1 Effect None Set Clear Toggle
* ACPC: RC Compare Effect on TIOA
ACPC 0 0 1 1 0 1 0 1 Effect None Set Clear Toggle
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* AEEVT: External Event Effect on TIOA
AEEVT 0 0 1 1 0 1 0 1 Effect None Set Clear Toggle
* ASWTRG: Software Trigger Effect on TIOA
ASWTRG 0 0 1 1 0 1 0 1 Effect None Set Clear Toggle
* BCPB: RB Compare Effect on TIOB
BCPB 0 0 1 1 0 1 0 1 Effect None Set Clear Toggle
* BCPC: RC Compare Effect on TIOB
BCPC 0 0 1 1 0 1 0 1 Effect None Set Clear Toggle
* BEEVT: External Event Effect on TIOB
BEEVT 0 0 1 1 0 1 0 1 Effect None Set Clear Toggle
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* BSWTRG: Software Trigger Effect on TIOB
BSWTRG 0 0 1 1 0 1 0 1 Effect None Set Clear Toggle
TC Counter Value Register
Register Name: Access Type:
31 - 23 - 15 30 - 22 - 14
TC_CVR Read-only
29 - 21 - 13 28 - 20 - 12 CV 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 CV
3
2
1
0
* CV: Counter Value CV contains the counter value in real-time.
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TC Register A
Register Name: Access Type:
31 - 23 - 15 30 - 22 - 14
TC_RA Read-only if WAVE = 0, Read/Write if WAVE = 1
29 - 21 - 13 28 - 20 - 12 RA 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 RA
3
2
1
0
* RA: Register A RA contains the Register A value in real-time.
TC Register B
Register Name: Access Type:
31 - 23 - 15 30 - 22 - 14
TC_RB Read-only if WAVE = 0, Read/Write if WAVE = 1
29 - 21 - 13 28 - 20 - 12 RB 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 RB
3
2
1
0
* RB: Register B RB contains the Register B value in real-time.
TC Register C
Register Name: Access Type:
31 - 23 - 15 30 - 22 - 14
TC_RC Read/Write
29 - 21 - 13 28 - 20 - 12 RC 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 RC
3
2
1
0
* RC: Register C RC contains the Register C value in real-time.
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TC Status Register
Register Name: Access Type:
31 - 23 - 15 - 7 ETRGS 30 - 22 - 14 - 6 LDRBS
TC_SR Read-only
29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 MTIOB 10 - 2 CPAS 25 - 17 MTIOA 9 - 1 LOVRS 24 - 16 CLKSTA 8 - 0 COVFS
* COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. * LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register if WAVE = 0. * CPAS: RA Compare Status 0 = RA compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA compare has occurred since the last read of the Status Register if WAVE = 1. * CPBS: RB Compare Status 0 = RB compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB compare has occurred since the last read of the Status Register if WAVE = 1. * CPCS: RC Compare Status 0 = RC compare has not occurred since the last read of the Status Register. 1 = RC compare has occurred since the last read of the Status Register. * LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. * LDRBS: RB Loading Status 0 = RB load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB load has occurred since the last read of the Status Register if WAVE = 0. * ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. * CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. * MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, then TIOA pin is low. If WAVE = 1, then TIOA is driven low. 1 = TIOA is high. If WAVE = 0, then TIOA pin is high. If WAVE = 1, then TIOA is driven high.
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* MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, then TIOB pin is low. If WAVE = 1, then TIOB is driven low. 1 = TIOB is high. If WAVE = 0, then TIOB pin is high. If WAVE = 1, then TIOB is driven high.
TC Interrupt Enable Register
Register Name: Access Type:
31 - 23 - 15 - 7 ETRGS 30 - 22 - 14 - 6 LDRBS
TC_IER Write-only
29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
* COVFS: Counter Overflow * LOVRS: Load Overrun * CPAS: RA Compare * CPBS: RB Compare * CPCS: RC Compare * LDRAS: RA Loading * LDRBS: RB Loading * ETRGS: External Trigger 0 = No effect. 1 = Enables the corresponding interrupt.
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TC Interrupt Disable Register
Register Name: Access Type:
31 - 23 - 15 - 7 ETRGS 30 - 22 - 14 - 6 LDRBS
TC_IDR Write-only
29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
* COVFS: Counter Overflow * LOVRS: Load Overrun * CPAS: RA Compare * CPBS: RB Compare * CPCS: RC Compare * LDRAS: RA Loading * LDRBS: RB Loading * ETRGS: External Trigger 0 = No effect. 1 = Disables the corresponding interrupt.
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TC Interrupt Mask Register
Register Name: Access Type:
31 - 23 - 15 - 7 ETRGS 30 - 22 - 14 - 6 LDRBS
TC_IMR Read-only
29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
* COVFS: Counter Overflow * LOVRS: Load Overrun * CPAS: RA Compare * CPBS: RB Compare * CPCS: RC Compare * LDRAS: RA Loading * LDRBS: RB Loading * ETRGS: External Trigger 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
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Serial Peripheral Interface (SPI)
The AT91C140 embeds a Serial Peripheral Interface featuring: * * * * * * * * * * * * Four Chip Selects with External Decoder Support Allowing Communication with Up to 15 Peripherals Serial Memories, such as DataFlash and 3-wire EEPROMS Serial Peripherals, such as ADCS, DACS, LCD Controllers, CAN Controllers And Sensors External Co-processors Master or Slave Serial Peripheral Bus Interface 8- to 16-bit Programmable Data Length Per Chip Select Programmable Phase and Polarity Per Chip Select Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data Per Chip Select Programmable Delay Between Consecutive Transfers Selectable Mode Fault Detection Connection to PDC Channel Capabilities Optimizes Data Transfers One Channel for the Receiver, One Channel for the Transmitter
Overview
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also allows communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the "master"' that controls the data flow, while the other system acts as the "slave'' that has data shifted into and out of it by the master. Different CPUs can take turn being masters (Multiple Master Protocol versus Single Master Protocol, where one CPU is always the master while all of the others are always slaves), and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
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Block Diagram
Figure 34. Block Diagram
ASB
APB Bridge
PDC APB SPCK MISO MOSI SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3
ACK ACK/32
SPI Interrupt
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Connections
Figure 35. Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS
SPCK MISO Slave 2 MOSI NSS
Pin Name List
Table 33. I/O Lines Description
Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Type I/O I/O I/O Input I/O Mode Master Slave Master Slave Master Slave Master Master Master Slave Comments Serial data input to SPI Serial data output from SPI Serial data output from SPI Serial data input to SPI Clock output from SPI Clock input to SPI Select peripherals Output: Selects peripheral Input: low causes mode fault Input: chip select for SPI
Master Mode Operations
When configured in Master Mode, the Serial Peripheral Interface controls data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select(s) to the slave(s) and the serial clock (SPCK). After enabling the SPI, a data transfer begins when the core writes to the SPI_TDR (Transmit Data Register). Transmit and Receive buffers maintain the data flow at a constant rate with a reduced requirement for high-priority interrupt servicing. When new data is available in the
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SPI_TDR, the SPI continues to transfer data. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error (OVRES) flag is set.
Note: As long as this flag is set, no data is loaded in the SPI_RDR. The user has to read the status register to clear it.
The delay between the activation of the chip select and the start of the data transfer (DLYBS), as well as the delay between each data transfer (DLYBCT), can be programmed for each of the four external chip selects. All data transfer characteristics, including the two timing values, are programmed in registers SPI_CSR0 to SPI_CSR3 (Chip Select Registers). In Master Mode, the peripheral selection can be defined in two different ways: * * Fixed Peripheral Select: SPI exchanges data with only one peripheral Variable Peripheral Select: Data can be exchanged with more than one peripheral
Figure 39 and Figure 40 show the operation of the SPI in Master Mode. For details concerning the flag and control bits in these diagrams, see "SPI Chip Select Register" on page 157. Fixed Peripheral Select This mode is used for transferring memory blocks without the extra overhead in the transmit data register to determine the peripheral. Fixed Peripheral Select is activated by setting bit PS to zero in SPI_MR (Mode Register). The peripheral is defined by the PCS field in SPI_MR. This option is only available when the SPI is programmed in Master Mode. Variable Peripheral Select Variable Peripheral Select is activated by setting the PS bit to one. The PCS field in SPI_TDR is used to select the destination peripheral. The data transfer characteristics are changed when the selected peripheral changes, depending on the associated chip select register. The PCS field in the SPI_MR has no effect. This option is available only when the SPI is programmed in Master Mode. Chip Selects The Chip Select lines are driven by the SPI only if it is programmed in Master Mode. These lines are used to select the destination peripheral. The PCSDEC field in SPI_MR (Mode Register) selects one to four peripherals (PCSDEC = 0) or up to 15 peripherals (PCSDEC = 1). If Variable Peripheral Select is active, the chip select signals are defined for each transfer in the PCS field in SPI_TDR. Chip select signals can thus be defined independently for each transfer. If Fixed Peripheral Select is active, Chip Select signals are defined for all transfers by the field PCS in SPI_MR. If a transfer with a new peripheral is necessary, the software must wait until the current transfer is completed, then change the value of PCS in SPI_MR before writing new data in SPI_TDR. The value on the NPCS pins at the end of each transfer can be read in the SPI_RDR (Receive Data Register). By default, all NPCS signals are high (equal to one) before and after each transfer. Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS[0]/NSS signal.
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When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is disabled until re-enabled by bit SPIEN in the SPI_CR (Control Register). By default, Mode Fault Detection is enabled. It is disabled by setting the MODFDIS bit in the SPI Mode Register.
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Master Mode Flow Diagram Figure 36. Master Mode Flow Diagram
SPI Enable
1 TDRE 0 0 PS 1 Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral
NPCS = SPI_TDR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD) TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer RDRF = 1
Delay DLYBCT
TDRE
0
1 NPCS = 0xF
PS 1
0 Fixed peripheral
Variable peripheral Same peripheral
Delay DLYBCS SPI_TDR(PCS) New peripheral NPCS = 0xF
Delay DLYBCS
NPCS = SPI_TDR(PCS)
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Master Mode Block Diagram Figure 37. Master Mode Block Diagram
SPI_MR(DIV32) ACK
0 1 SPI Master Clock
SPCK Clock Generator SPI_CSRx[15:0] SPCK
ACK/32
SPIDIS
SPIEN S Q R
SPI_RDR PCS LSB MISO
RD MSB MOSI
Serializer
SPI_TDR PCS
TD NPCS3 NPCS2
SPI_MR(PS)
NPCS1 NPCS0
1 SPI_MR(PCS) 0
SPI_MR(MSTR) SPI_SR M O D F T D R E R D R F O V R E S P I E N S
SPI_IER SPI_IDR SPI_IMR
SPI Interrupt
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SPI Slave Mode
In Slave Mode, the SPI waits for NSS to go active low before receiving the serial clock from an external master. In Slave Mode, CPOL, NCPHA and BITS fields of SPI_CSR0 are used to define the transfer characteristics. The other Chip Select Registers are not used in Slave Mode.
Figure 38. Slave Mode Block Diagram
SPCK
NSS
SPIDIS
SPIEN S Q R
SPI_RDR RD LSB MOSI MSB MISO
Serializer
SPI_TDR TD
SPI_SR
S P I E N S
T D R E
R D R F
O V R E
SPI_IER SPI_IDR SPI_IMR
SPI Interrupt
Data Transfers
Four modes are used for data transfers. These modes correspond to combinations of a pair of parameters called clock polarity (CPOL) and clock phase (CPHA) that determine the edges of the clock signal on which the data are driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus a master/slave pair must use the same parameter
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pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 34 shows the four modes and corresponding parameter settings. Table 34. SPI Bus Protocol Mode
SPI Mode 0 1 2 3 CPOL 0 0 1 1 CPHA 0 1 0 1
Figure 39 and Figure 40 show examples of data transfers. Figure 39. SPI Transfer Format (NCPHA = 1, 8 bits per transfer
SPCK cycle (for reference) SPCK (CPOL=0) 1 2 3 4 5 6 7 8
SPCK (CPOL=1)
MOSI (from master)
MSB
6
5
4
3
2
1
LSB
MISO (from slave)
MSB
6
5
4
3
2
1
LSB
*
NSS (to slave)
* Not defined, but normally MSB of previous character received.
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Figure 40. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
SPCK cycle (for reference) SPCK (CPOL=0) 1 2 3 4 5 6 7 8
SPCK (CPOL=1)
MOSI (from master)
MSB
6
5
4
3
2
1
LSB
MISO (from slave)
*
MSB
6
5
4
3
2
1
LSB
NSS (to slave)
* Not defined but normally LSB of previous character transmitted.
Clock Generation
In Master Mode, the SPI Master Clock is either CLOCK or FDIV, as defined by the DIV32 field of SPI_MR. The SPI baud rate clock is generated by dividing the SPI Master Clock by a value between 4 and 510. The divisor is defined in the SCBR field in each Chip Select Register. The transfer speed can thus be defined independently for each chip select signal. CPOL and NCPHA in the Chip Select Registers define the clock/data relationship between master and slave devices. CPOL defines the inactive value of the SPCK. NCPHA defines which edge causes data to change and which edge causes data to be captured. In Slave Mode, the input clock low and high pulse duration must be longer than two system clock (CLOCK) periods.
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Serial Peripheral Interface (SPI) User Interface
Table 35. SPI Memory Map
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Pointer Register Receive Counter Register Transmit Pointer Register Transmit Counter Register Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Register Register Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR SPI_RPR SPI_RCR SPI_TPR SPI_TCR SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset --0x0 0x0 --0x000000F0 ----0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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SPI Control Register
Name: SPI_CR Access Type: Write-only
31 30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
SWRST
-
-
-
-
-
SPIDIS
SPIEN
* SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. * SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled * SWRST: SPI Software Reset 0 = No effect. 1 = Resets the SPI. A software-triggered hardware reset of the SPI interface is performed.
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SPI Mode Register
Name: Access Type:
31 30
SPI_MR Read/Write
29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
LLB
-
-
MODFDIS
DIV32
PCSDEC
PS
MSTR
* MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. * PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. * PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 15*. *Note: The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration to be defined by each chip select register. * DIV32: Clock Selection 0 = SPI Master Clock equals ACK. 1 = SPI Master Clock equals ACK/32. * MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. * LLB: Local Loopback Enable 0 = Local loopback path disabled 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only.
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* PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS * DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six SPI Master Clock periods will be inserted by default. Otherwise, the following equation determines the delay: NPCS_to_SCK_Delay = DLYBCS * SPI_Master_Clock_period NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected)
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SPI Receive Data Register
Name: Access Type:
31 30
SPI_RDR Read-only
29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
RD
7 6 5 4 3 2 1 0
RD
* RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. * PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.
SPI Transmit Data Register
Name: Access Type:
31 30
SPI_TDR Write-only
29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
TD
7 6 5 4 3 2 1 0
TD
* TD: Transmit Data Data to be transmitted by the SPI is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected)
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SPI Status Register
Name: Access Type:
31
SPI_SR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
SPIENS
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. * TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. * MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. * OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. * ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR. 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR. * ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR. 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR. * SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled.
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SPI Interrupt Enable Register
Name: Access Type:
31 30
SPI_IER Write-only
29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Enable * TDRE: SPI Transmit Data Register Empty Interrupt Enable * MODF: Mode Fault Error Interrupt Enable * OVRES: Overrun Error Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
SPI Interrupt Disable Register
Name: Access Type:
31 30
SPI_IDR Write-only
29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Disable * TDRE: SPI Transmit Data Register Empty Interrupt Disable * MODF: Mode Fault Error Interrupt Disable * OVRES: Overrun Error Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
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SPI Interrupt Mask Register
Name: Access Type:
31 30
SPI_IMR Read-only
29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Mask * TDRE: SPI Transmit Data Register Empty Interrupt Mask * MODF: Mode Fault Error Interrupt Mask * OVRES: Overrun Error Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
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SPI Chip Select Register
Name: Access Type:
31 30
SPI_CSR0... SPI_CSR3 Read/Write
29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS
-
-
NCPHA
CPOL
* CPOL: Clock Polarity 0 = The inactive state value of SCK is logic level zero. 1 = The inactive state value of SCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. * NCPHA: Clock Phase 0 = Data is changed on the leading edge of SCK and captured on the following edge of SCK. 1 = Data is captured on the leading edge of SCK and changed on the following edge of SCK. NCPHA determines which edge of SCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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* SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Master Clock (selected between CLOCK and FDIV). The Baud rate is selected by writing a value from 2 to 255 in the field SCBR. The following equation determines the SPCK baud rate: SPCK Baudrate = SPI_Master_Clock / (2 * SCBR) Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state value. No serial transfers may occur. At reset, baud rate is disabled. * DLYBS: Delay Before SCK This field defines the delay from NPCS valid to the first valid SCK transition. When DLYBS equals zero, the NPCS valid to SCK transition is 1/2 the SCK clock period. Otherwise, the following equation determines the delay: NPCS_to_SCK_Delay = DLYBS * SPI_Master_Clock_period * DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, a delay of four SPI Master Clock periods are inserted. Otherwise, the following equation determines the delay: Delay_After_Transfer = 32 * DLYBCT * SPI_Master_Clock_period.
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SPI Receive Pointer Register
Register Name: Access Type:
31 30
SPI_RPR Read/Write
29 28 RXPTR 27 26 25 24
23
22
21
20 RXPTR
19
18
17
16
15
14
13
12 RXPTR
11
10
9
8
7
6
5
4 RXPTR
3
2
1
0
* RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer.
SPI Receive Counter Register
Register Name: Access Type:
31 -23 -15 30 -22 -14
SPI_RCR Read/Write
29 -21 -13 28 -20 -12 RXCTR 27 -19 -11 26 -18 -10 25 -17 -9 24 -16 -8
7
6
5
4 RXCTR
3
2
1
0
* RXCTR: Receive Counter Register RXCTR must be loaded with the size of the receive buffer. 0 = Stops peripheral data transfer 1 - 65535 = Start peripheral data transfer if RDRF is active.
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SPI Transmit Pointer Register
Register Name: Access Type:
31 30
SP_TPR Read/Write
29 28 TXPTR 27 26 25 24
23
22
21
20 TXPTR
19
18
17
16
15
14
13
12 TXPTR
11
10
9
8
7
6
5
4 TXPTR
3
2
1
0
* TXPTR: Transmit Pointer Register TXPTR must be loaded with the address of the transmit buffer.
SPI Transmit Counter Register
Register Name: Access Type:
31 -23 -15 30 -22 -14
SP_TCR Read/Write
29 -21 -13 28 -20 -12 TXCTR 27 -19 -11 26 -18 -10 25 -17 -9 24 -16 -8
7
6
5
4 TXCTR
3
2
1
0
* TXCTR: Transmit Counter Register TXCTR must be loaded with the size of the receive buffer. 0 = Stops peripheral data transfer 1 - 65535 = Start peripheral data transfer if TDRE is active.
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Ordering Information
Table 36. Ordering Information
Ordering Reference AT91C140-CI Temp -40C to +85C Package BGA256
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Mechanical Characteristics and Packaging
BGA Packaging Information
Figure 41. AT91C140 BGA Package
b
For BGA package data, see Table 37 on page 163,
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BGA Package Data
Table 37. Dimensions (mm)
Symbol A1 b aaa bbb ccc ddd eee A B D/E D1/E1 e f 1.92 0.28 26.8 Min 0.50 0.60 Nom 0.60 0.75 0.30 0.25 0.35 0.30 0.15 2.13 0.32 27.0 24.0 1.27 8.05 2.34 0.38 27.2 24.7 Max 0.70 0.90
.
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Table of Contents
Features............................................................................................................ 1 Description....................................................................................................... 1 Block Diagram ................................................................................................. 2 Pinout ............................................................................................................... 3
256-ball BGA Package Pinout ......................................................................... 3 Mechanical Overview of the 256-ball BGA Package........................................ 5
Peripheral Multiplexing on PIO Lines ............................................................ 6
PIO Controller A Multiplexing .......................................................................... 7 PIO Controller B Multiplexing .......................................................................... 8
Signal Description .......................................................................................... 9 ARM7TDMI Core ............................................................................................ 12 Power Supplies .............................................................................................. 12 System Controller .......................................................................................... 12
Test ................................................................................................................ Reset Controller ............................................................................................. Clock Generator ............................................................................................. Chip ID ........................................................................................................... System Controller User Interface.................................................................... System Mode Register................................................................................... System ID Register ........................................................................................ System Clock Status Register........................................................................ 12 12 13 13 14 15 16 16
Memory Controller (MC)................................................................................ 17
Architecture .................................................................................................... Memory Map .................................................................................................. ARM ASB Arbitration...................................................................................... MAC ASB Arbitration...................................................................................... ASB-ASB Bridge Arbitration ........................................................................... Boot Mode...................................................................................................... Endianness .................................................................................................... 17 18 19 19 19 20 20
Peripherals ..................................................................................................... 21
Peripheral Registers....................................................................................... 21 Peripheral Memory Map ................................................................................. 22
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Peripheral Data Controller (PDC) ................................................................. 23
PDC Overview................................................................................................ 23 PDC Channel Priority ..................................................................................... 23
Boot Program ................................................................................................. 24
Boot Mode...................................................................................................... Hardware Connection of the DataFlash ......................................................... Internal Boot Software.................................................................................... DataFlash Header Details .............................................................................. Reserved Resources...................................................................................... 24 24 24 25 25
External Bus Interface (EBI) ......................................................................... 27
Signal Multiplexing ........................................................................................ 27
SDRAM Controller (SDRAMC) ...................................................................... 28
Description ..................................................................................................... Block Diagram................................................................................................ I/O Lines Description ..................................................................................... Application Example....................................................................................... SDRAM Device Initialization .......................................................................... SDRAM Controller Write Cycle ...................................................................... SDRAM Controller Read Cycle ...................................................................... Border Management ...................................................................................... SDRAM Controller Refresh Cycles ................................................................ SDRAM User Interface...................................................................................... SDRAMC Mode Register ............................................................................... SDRAMC Refresh Timer Register ................................................................. SDRAMC Configuration Register ................................................................... SDRAMC Address Register ........................................................................... 28 28 29 29 31 33 34 35 36 37 37 38 39 40
Static Memory Controller (SMC) .................................................................. 41
External Memory Mapping ............................................................................. Pin Description ............................................................................................... Data Bus Width .............................................................................................. Byte Write or Byte Select Mode ..................................................................... Read Protocols............................................................................................... Write Protocol................................................................................................. Wait States ..................................................................................................... Signal Waveforms .......................................................................................... SMC User Interface........................................................................................... SMC Chip Select Register ............................................................................. SMC Memory Control Register ...................................................................... 41 41 41 42 42 43 43 44 47 48 49
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Ethernet MAC (EMAC)................................................................................... 50
Block Diagram................................................................................................ Media Independent Interface ........................................................................ Transmit/Receive Operation .......................................................................... DMA Operations............................................................................................. Address Checking .......................................................................................... EMAC User Interface ........................................................................................ EMAC Control Register.................................................................................. EMAC Mode Register .................................................................................... EMAC Status Register ................................................................................... EMAC Transmit Address Register ................................................................. EMAC Transmit Control Register ................................................................... EMAC Transmit Status Register .................................................................... EMAC Receive Buffer Queue Pointer Register.............................................. EMAC Receive Status Register ..................................................................... EMAC Interrupt Status Register..................................................................... EMAC Interrupt Enable Register .................................................................... EMAC Interrupt Disable Register ................................................................... EMAC Interrupt Mask Register ...................................................................... EMAC PHY Maintenance Register ................................................................ EMAC Hash Address High Register .............................................................. EMAC Hash Address Low Register ............................................................... EMAC Specific Address (1, 2, 3 and 4) High Register ................................... EMAC Specific Address (1, 2, 3 and 4) Low Register.................................... EMAC Statistics Register Block Registers ..................................................... 50 51 51 53 55 57 58 59 60 60 61 62 63 63 64 65 66 67 68 69 69 70 70 71
Advanced Interrupt Controller (AIC) ............................................................ 72
Priority Controller ........................................................................................... Interrupt Handling........................................................................................... Standard Interrupt Sequence ......................................................................... Fast Interrupt.................................................................................................. Software Interrupt........................................................................................... Spurious Interrupt........................................................................................... AIC User Interface............................................................................................. AIC Source Mode Register ............................................................................ AIC Interrupt Vector Registers ....................................................................... AIC FIQ Vector Register ................................................................................ AIC Interrupt Status Register ......................................................................... AIC Interrupt Mask Register ........................................................................... AIC Core Interrupt Status Register ................................................................ AIC Interrupt Enable Command Register....................................................... AIC Interrupt Disable Command Register ...................................................... AIC Interrupt Clear Command Register ......................................................... AIC Interrupt Set Command Register ............................................................ AIC End of Interrupt Command Register ....................................................... 73 73 74 75 75 76 77 78 79 79 80 80 81 81 82 82 83 83
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6069A-ATARM-05/04
AIC Spurious Interrupt Vector Register .......................................................... 84
Parallel I/O Controller (PIO) .......................................................................... 85
Output Selection............................................................................................. I/O Levels ....................................................................................................... Interrupts ........................................................................................................ I/O Line Control .............................................................................................. Parallel I/O Controller (PIO) User Interface .................................................... PIO Enable Register ...................................................................................... PIO Disable Register...................................................................................... PIO Status Register ....................................................................................... PIO Output Enable Register........................................................................... PIO Output Disable Register .......................................................................... PIO Output Status Register............................................................................ PIO Set Output Data Register ........................................................................ PIO Clear Output Data Register..................................................................... PIO Output Data Status Register ................................................................... PIO Pin Data Status Register......................................................................... PIO Interrupt Enable Register ........................................................................ PIO Interrupt Disable Register ....................................................................... PIO Interrupt Mask Register........................................................................... PIO Interrupt Status Register ......................................................................... 85 85 85 86 87 88 88 89 89 90 90 91 91 92 92 93 93 94 94
Universal Asynchronous Receiver Transmitter (UART) ............................ 95
Block Diagram................................................................................................ 95 Pin Description ............................................................................................... 96 Baud Rate Generator ..................................................................................... 96 Receiver Operations ...................................................................................... 97 Transmitter ..................................................................................................... 98 Channel Modes .............................................................................................. 98 Peripheral Data Controller.............................................................................. 99 Modem Control and Status Signals.............................................................. 100 Universal Asynchronous Receiver/Transmitter (UART) User Interface .... 101 UART Control Register ................................................................................ 102 UART Mode Register ................................................................................... 103 UART Interrupt Enable Register .................................................................. 105 UART Interrupt Disable Register.................................................................. 106 UART Interrupt Mask Register ..................................................................... 107 UART Channel Status Register ................................................................... 108 UART Receiver Holding Register................................................................. 109 UART Transmitter Holding Register............................................................. 109 UART Baud Rate Generator Register .......................................................... 110 UART Receive Pointer Register................................................................... 110 UART Receive Counter Register ................................................................. 111 UART Transmit Pointer Register.................................................................. 111
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AT91C140
6069A-ATARM-05/04
AT91C140
UART Transmit Counter Register ................................................................ 112 Modem Control Register .............................................................................. 112 Modem Status Register................................................................................ 113
Timer/Counter (TC)...................................................................................... 114
Block Diagram.............................................................................................. Signal Name Description.............................................................................. Description ................................................................................................... Capture Operating Mode.............................................................................. Waveform Operating Mode .......................................................................... Timer/Counter (TC) User Interface ................................................................ TC Block Control Register............................................................................ TC Block Mode Register .............................................................................. TC Channel Control Register ....................................................................... TC Channel Mode Register: Capture Mode................................................. TC Channel Mode Register: Waveform Mode ............................................. TC Counter Value Register .......................................................................... TC Register A............................................................................................... TC Register B............................................................................................... TC Register C .............................................................................................. TC Status Register....................................................................................... TC Interrupt Enable Register ....................................................................... TC Interrupt Disable Register....................................................................... TC Interrupt Mask Register .......................................................................... 115 115 116 119 120 124 125 126 127 128 130 133 134 134 134 135 136 137 138
Serial Peripheral Interface (SPI) ................................................................. 139
Overview ...................................................................................................... Block Diagram.............................................................................................. Connections ................................................................................................. Pin Name List .............................................................................................. Master Mode Operations.............................................................................. SPI Slave Mode ........................................................................................... Data Transfers ............................................................................................. Clock Generation ......................................................................................... Serial Peripheral Interface (SPI) User Interface ........................................... SPI Control Register .................................................................................... SPI Mode Register ....................................................................................... SPI Receive Data Register .......................................................................... SPI Transmit Data Register ......................................................................... SPI Status Register ...................................................................................... SPI Interrupt Enable Register ...................................................................... SPI Interrupt Disable Register...................................................................... SPI Interrupt Mask Register ......................................................................... SPI Chip Select Register.............................................................................. SPI Receive Pointer Register....................................................................... 139 140 141 141 141 146 146 148 149 150 151 153 153 154 155 155 156 157 159
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6069A-ATARM-05/04
SPI Receive Counter Register ..................................................................... SPI Transmit Pointer Register...................................................................... SPI Transmit Counter Register .................................................................... Ordering Information...................................................................................... Mechanical Characteristics and Packaging ................................................. BGA Packaging Information ......................................................................... BGA Package Data ...................................................................................... Document Details ........................................................................................... Revision History ...........................................................................................
159 160 160 161 162 162 163 164 164
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AT91C140
6069A-ATARM-05/04
Atmel Corporation
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6069A-ATARM-05/04

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